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ks57c 0502/c0504/p0504 microcontroller product overview 1? 1 1 product overview the ks57c 0502/c0504 single-chip cmos microcontroller has been designed for high-performance using samsung's newest 4 -bit cp u core, sam47 ( samsung arrangeable microcontrollers). the ks57p0504 is the microcontroller which has 4 kbyte one-time-programmable rom and the functions are the same to KS57C0502/c0504. with a four-channel comparator, eight led direct drive pins, serial i/o interface, and its ver satile 8-bit timer/counter, the ks57 c0502/c0504 offers an excel lent design solution for a wide variety of general-purpose applica tions. up to 24 pins of the 30-pin sdip package can be dedicated to i/o. five vectored interrupts provide fast re - sponse to internal and external events. in addition, the ks57c 0502/c0504 's advanced cmos technol ogy provides for very low power consumption and a wide op erating voltage range ? all at a very low cost. features summary memory 512 4-bit data memory (ram) 2048 8-bit program memory (rom) :KS57C0502 4096 8-bit program memory (rom) :ks57c0504 24 i/o pins i/o: 18 pins, including 8 high current pins input only: 6 pins comparator 4-channel mode: internal reference (4-bit resolution) 16-s tep variable reference voltage 3-channel mode: external reference 150 mv resolution (worst case) 8-bit basic timer programmable interval timer watch-dog timer 8-bit timer/counter programmable interval timer external event counter function timer/counter clock output to tclo0 pin watch timer time interval generation: 0.5 s, 3.9 ms at 4.19 m hz 4 frequency outputs to buz pin 8-bit serial i/o interface 8-bit transmit/receive mode 8-bit receive-only mode lsb-first or msb-first transmission selectable internal or external clock source bit sequential carrier supports 16-bit serial data transfer in arbitrary format interrupts two external interrupt vectors three internal interrupt vectors two quasi-interrupts memory-mapped i/o structure data memory bank 15 two power-down modes idle mode: only cpu clock stops stop mode: system clock stops oscillation sources crystal, ceramic for system clock crystal/ceramic: 0.4 - 6.0 mhz cpu clock divider circuit (by 4. 8, or 64) instruction execution times 0.95, 1.91, 15.3 s at 4.19 mhz 0. 67 , 1. 33 , 1 0.7 s at 6.0 mhz operating temperature ? 40 c to 85 c operating voltage range 1.8 v to 5.5 v package type 30 sdip , 32 sop
product overview ks57c 0502/c0504/p0504 microcontroller 1? 2 function overview sam47 cpu all ks57-series microcontrollers have the advanced sam47 cpu core. the sam47 cpu can directly address up to 32 k bytes of program memory. the arithmetic logic unit (alu) performs 4-bit addition, subtraction, logical, and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two cycles. cpu registers program counter a 11-bit program counter (pc) stores addresses for instruction fetch during program execution. usually, the pc is incremented by the number of bytes of the instruction being fetched. an exception is the 1-byte instruction ref which is used to reference instructions stored in a look-up table in the rom. whenever a reset operation or an interrupt occurs, bits pc1 1 through pc0 are set to the vector address. bit pc13?1 2 is reserved to support future expan sion of the device's rom size. stack pointer an 8-bit stack pointer (sp) stores addresses for stack operations. the stack area is located in the general- purpose data memory bank 0. the sp is read or written by 8-bit instructions and sp bit 0 must always be set to logic zero. during an interrupt or a subroutine call, the pc value and the psw are saved to the stack area in ram. when the service routine has completed, the values referenced by the stack pointer are restored. then, the next instruc ti on is exe cuted. the stack pointer can access the stack regardless of data memory access enable flag status. since the reset value of the stack pointer is not de fined in firmware, it is recommended that the stack pointer be initialized to 00h by program code. this sets the first register of the stack area to data mem ory location 0ffh. program memory in its standard configuration, the 4096 8-bit rom is divided into three functional areas: ? 16-byte area for vector addresses ? 96-byte instruction referenc e area ? 1920-byte general purpose area (KS57C0502) ? 3968-byte general purpose area (ks57c0504) the vector address area is used mostly during reset operations and interrupts. these 16 bytes can also be used as general-purpose rom. the ref instruction references 2 1 -byte and 2 -byte instructions stored in locations 0020h ?007fh. the ref instruction can also reference three-byte instructions such as jp or call. in order for ref to be able to reference these instructions, however, jp or call must be shortened to a 2-byte format. to do this, jp or call is is written to the reference area with the format tjp or tcall instead of the normal instruction name. unused locations in the instruction reference area can be allocated to general-purpose use.
ks57c 0502/c0504/p0504 microcontroller product overview 1? 3 data memory overview data memory is organized into three areas: ? 32 4-bit working registers ? 224 4 -bit general-purpose area in bank 0 ? 256 4 -bit general-purpose area in bank 1 ? 128 4-bit area in bank 15 for memory-mapped i/o addresses data stored in data memory can be manipulated by 1-, 4-, and 8-bit instructions. data memory is organized into two memory banks ? bank 0, bank 1 and bank 15. the select memory bank in struction (smb) selects the bank to be used as work ing data memory. after power-on reset operation, initialization values for data memory must be redefined by code. data memory addressing modes the enable memory bank (emb) flag controls the addressing mode for data memory banks 0 , 1 or 15. when the emb flag is logic zero, restricted area can be accessed. when the emb flag is set to logic one, all two data memory banks can be ac cessed ac cording to the current smb value. the emb = "0" addressing mode is used for nor mal program execution, whereas the emb = "1" mode is commonly used for interrupts, subroutines, mapped i/o, and repetitive access of specific ram addresses. working registers the ram's working register area in data memory bank 0 is further divided into four register banks. each register bank has eight 4-bit registers that are addressable either by 1-bit or 4 -bit instructions. paired 4-bit registers can be addressed as double registers by 8-bit instructions. register a is the 4-bit accumulator and double register ea is the 8-bit extended accumulator. double registers wx, wl, and hl are used as data pointers for indirect addressing. unused working reg isters can be used as general-purpose memory. to limit the possibility of data corruption due to in correct register bank addressing, register bank 0 is usually used by the main program and banks 1, 2, and 3 for interrupt service routines.
product overview ks57c 0502/c0504/p0504 microcontroller 1? 4 control registers program status word the 8-bit program status word (psw) controls alu operations and instruction execution sequencing. it is also used to restore a program's execution environment when an interrupt has been serviced. program instructions can always address the psw regardless of the current value of data memory enable flags. before an interrupt or subroutine is processed, the psw is pushed onto the stack in data memory bank 0. when the service routine is completed, the psw values are restored. is1 is0 emb erb c sc2 sc1 sc0 interrupt status flags (is1, is0), the enable memory bank and enable register bank flags (emb, erb), and the carry flag (c) are 1 - and 4-bit read/write or 8-bit read-only addressable. you can address the skip condition flags (sc0?sc2) using 8-bit read instructions only. select bank (sb) register two 4-bit registers store address values used to access specific memory and register banks: the select memory bank register, smb, and the select register bank reg ister, srb. 'smb n' instruction selects a data memory bank (0 or 15) and stores the upper four bits of the 12-bit data memory address in the smb register. to select register bank 0, 1, 2, or 3, and store the ad dress data in the srb, you use the instruction 'srb n'. the instructions "push sb" and "pop sb" move srb and smb values to and from the stack for interrupts and subroutines. clock circuits system oscillation circuit generates the internal clock signals for the cpu and peripheral hardware. the system c lock can use a crystal, or ceramic oscillation source, or an externally-generated clock signal. to drive KS57C0502/c0504 using an external clock source, the external clock signal should be input to x in , and its inverted signal to x out . 4 -bit power control register controls the oscillation on/off, and select the cpu clock. the internal system clock signal ( fx) can be divided internally to produce three cpu clock frequencies ? fx/4, fx/8, or fx/64. interrupts interrupt requests may be generated internally by on-chip processes (intb, intt0, and ints) or externally by peripheral devices (int0 and int1). there are two quasi-interrupts: intk and intw. intk (ks0?ks2) detects falling edges of incoming signals and intw detects time intervals of 0.5 seconds or 3.91 milliseconds. the following components support interrupt processing: ? interrupt enable flags ? interrupt request flags ? interrupt priority registers ? power-down termination circuit
ks57c 0502/c0504/p0504 microcontroller product overview 1? 5 power-down to reduce power consumption, there are two power-down modes: idle and stop. the idle instruction initiates idle mode; the stop instruction initiates stop mode. in idle mode, the cpu clock stops while peripher als continue to operate normally. in stop mode, system clock oscillation stops completely, halting all operations except for a few basic peripheral functions. a power-down is terminated either by a reset or by an interrupt (with exception of the external interrupt int0). reset when reset is input during normal operation or during power-down mode, a reset operation is initi ated and the cpu enters idle mode. when the standard oscillation stabilization time in terval (31.3 ms at 4.19 mhz) has elapsed, normal cpu operation resumes. i/o ports the KS57C0502/c0504 has seven i/o ports. pin addresses for all i/o ports are mapped to locations ff0h? ff 6 h in bank 15 of the ram. there are 6 input pins and 18 configurable i/o pins including 8 high current i/o pins for a total of 24 i/o pins. the contents of i/o port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. timers and timer/counter the timer function has three main components: an 8-bit basic timer, an 8-bit timer/counter, and a watch timer. the 8-bit basic timer generates interrupt requests at precise intervals, based on the selected internal clock frequency. the programmable 8-bit timer/counter is used for counting events, modifying internal clock frequencies, and dividing external clock signals. the 8-bit timer/counter generates a clock signal ( sck ) for the serial i/o interface. the watch timer consists of an 8-bit watch timer mode register, a clock selector, and a frequency di vider circuit. its functions include real-time, watch-time measurement, and clock generation for fre quency output for buzzer sound. serial i/o interface the serial i/o interface supports the transmission or reception of 8 -bit serial data with an external device. the serial interface has the following functional components: ? 8-bit mode register ? clock selector circuit ? 8-bit buffer register ? 3-bit serial clo ck counter the serial i/o circuit can be set to transmit-and-re ceive, or to receive-only mode. msb-first or lsb-first transmission is also selectable. the serial interface can operate with an internal or an external clock source, or using the clock signal generated by the 8-bit timer/counter. transmission frequency can be modified by setting the appropriate bits in the sio mode register.
product overview ks57c 0502/c0504/p0504 microcontroller 1? 6 bit sequential carrier the bit sequential carrier (bsc) is a 16-bit register that can be manipulated using 1-, 4-, and 8-bit instructions. using 1-bit indirect addressing, addresses and bit locations can be specified sequentially. in this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value of the l register. bsc data can also be manipulated using direct addressing. comparator the KS57C0502/c0504 contains a 4-channel comparator which can be multiplexed to normal input port. ? conversion time: 15.2 s, 121.6 s at 4.19 mhz ? two operation modes: three channels for analog input and one channel for external reference voltage input four channels for analog input and internal reference voltage level ? 16-level internal reference voltage generator ? 150 mv accuracy for input voltage level difference detection (maximum) ? comparator enable and disable the comparison results are read from the 4-bit cmpreg register after the specified conversion time.
ks57c 0502/c0504/p0504 microcontroller product overview 1? 7 block diagram p3.0 / tcl0 p3.1 / tclo0 p3.2 / clo arithmetic logic unit interrupt control block stack pointer program counter program status word i/o port 0 p0.0 / sck p0.1 / so p0.2 / si 512 x 4-bit data memory serial i/o port flags instruction decoder clock reset xin xout internal interrupts p4.0?p4.3 p5.0?p5.3 p6.0 / ks0 p6.1 / ks1 p6.2 / ks2 p6.3 / buz comparator input port 2 input port 1 p1.0 / int0 p1.1 / int1 p2.0 / cin0 p2.1 / cin1 p2 . 2 / cin2 p2.3 / cin3 program memory KS57C0502: 2 kbyte ks57c0504: 4 kbyte 8-bit timer/ counter i/o port 4 i/o port 5 i/o port 6 i/o port 3 basic timer watch timer figure 1? 1 . KS57C0502/c0504 simplified block diagram
product overview ks57c 0502/c0504/p0504 microcontroller 1? 8 pin assignments v dd p6.3 / buz p6.2 / ks2 p6.1 / ks1 p6.0 / ks0 p5.3 p5.2 p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 p3.2 / clo p3.1 / tclo0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 KS57C0502/0504 (top view) v ss xout xin test p1.0 / int0 p1.1 / int1 reset p0.0 / sck p0.1 / so p0.2 / si p2.0 / cin0 p2.1 / cin1 p2.2 / cin2 p2.3 / cin3 p3.0 / tcl0 30-pin sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 KS57C0502/0504 (top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32-pin sop v ss xout xin test p1.0 / int0 p1.1 / int1 reset nc p0.0 / sck p0.1 / so p0.2 / si p2.0 / cin0 p2.1 / cin1 p2.2 / cin2 p2.3 / cin3 p3.0 / tcl0 v dd p6.3 / buz p6.2 / ks2 p6.1 / ks1 p6.0 / ks0 p5.3 p5.2 p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 nc p3.2 / clo p3.1 / tclo0 figure 1? 2 . KS57C0502/c0504 pin assignment diagram
ks57c 0502/c0504/p0504 microcontroller product overview 1? 9 pin descriptions table 1?2. KS57C0502/c0504 pin descriptions pin name pin type description number share pin p0.0 p0.1 p0.2 i/o 3-bit i/o port. 1-bit or 3-bit read/write and test is possible. pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. pins are individually configurable as input or output. 8(9) 9(10) 10(11) sck so si p1.0 p1.1 i 2-bit input port. 1-bit or 2-bit read and test is possible. pull-up resistors are assignable by software. 5(5) 6(6) int0 int1 p2.0?p2.3 i 4-bit input port. 1-bit or 4-bit read and test is possible. 11-14 (12-15) cin0?cin3 p3.0 p3.1 p3.2 i/o same as port 0 15(16) 16(17) 17(18) tcl0 tclo0 clo p4.0?p4.3 p5.0?p5.3 i/o 4-bit i/o ports. 1-, 4-, or 8-bit read/write and test is possible. pins are individually configurable as input or output. 4-bit pull-up resistors are software assignable to input pins and are automatically disabled for output pins. the n-channel open-drain or push-pull output can be selected by software (1-bit unit) 18-21(20-23) 22-25(24-27) ? p6.0 p6.1 p6.2 p6.3 i/o 4-bit i/o port. 1-bit or 4-bit read/write and test is possible. pull-up resistors are assignable to input pins by software and are automatically disabled for output pins. pins are individually configurable as input or output. 26(28) 27(29) 28(30) 29(31) ks0 ks1 ks2 buz int0 i external interrupts with detection of rising and falling edges 5(5) p1.0 int1 i external interrupts with detection of rising or falling edges 6(6) p1.1 cin0?cin3 i 4-channel comparator input. cin0?cin2: compara tor input only. cin3: comparator input or external reference input 11-14(12-15) p2.0?p2.3 sck i/o serial interface clock signal 8(9) p0.0 so i/o serial data output 9(10) p0.1 si i/o serial data input 10(11) p0.2 tcl0 i/o external clock input for timer/counter 15(16) p3.0 tclo0 i/o timer/counter clock output 16(17) p3.1 clo i/o cpu clock output 17(18) p3.2 buz i/o 2 khz, 4 khz, 8 khz, or 16 khz frequency output at 4.19 mhz for buzzer sound 29(31) p6.3 note : pin numbers shown in parentheses '( )' are for 32-pin sop package; other pin numbers are for the 30-pin sdip.
product overview ks57c 0502/c0504/p0504 microcontroller 1? 10 table 1?2. KS57C0502/c0504 pin descriptions (continued) pin name pin type description number share pin ks0?ks2 i/o quasi-interrupt input with falling edge detection 26-28(28-30) p6.0?p6.2 v dd ? main power supply 30(32) ? v ss ? ground 1(1) ? reset i reset signal 7(7) ? test i test signal input (must be connected to v ss ) 4(4) ? x in , x out ? crystal or ceramic oscillator signal for system clock 3,2(3,2) ? note : pin numbers shown in parentheses '( )' are for 32-pin sop package; other pin numbers are for the 30-pin sdip. table 1?3. overview of KS57C0502/c0504 pin data sdip pin numbers pin names share pins i/o type reset value circuit type 1 v ss ? ? ? ? 2,3 xout , xin ? ? ? ? 4 test ? i ? ? 5,6 p1.0, p1.1 int0, int1 i input a-3 7 reset ? i ? b 8-10 p0.0 - p0.2 sck , so, si i/o input d-1 11-14 p2.0 - p2.3 cin0 - cin3 i input f-1 , f-2 (note) 15-17 p3.0 - p3.2 tcl0, tclo0, clo i/o input d-1 18-21 p4.0 - p4.3 ? i/o input e 22-25 p5.0 - p5.3 ? i/o input e 26 -29 p6.0 - p6.3 ks0, ks1, ks2, buz i/o input d-1 30 v dd ? ? ? ? note : i/o circuit type f-2 is implemented for p2.3 only.
ks57c 0502/c0504/p0504 microcontroller product overview 1? 11 pin circuit diagrams v dd p - channel in n - channel figure 1? 3 . pin circuit type a p - channel resistor enable v dd pull-up resistor schmitt trigger in figure 1? 4 . pin circuit type a- 3 v dd pull-up resistor schmitt trigger in figure 1? 5 . pin circuit type b data output disable out v dd p - channel n - channel figure 1? 6 . pin circuit type c
product overview ks57c 0502/c0504/p0504 microcontroller 1? 12 v dd pull-up resistor p - channel circuit type 4 resistor enable data output disable schmitt triger i/o figure 1? 7 . pin circuit type d-1 data output disable v dd p - channel pull-up resistor enable n - channel pne v dd pull-up resistor i/o figure 1? 8 . pin circuit type e digital input analog input figure 1? 9 . pin circuit type f-1 digital input analog input external v ref figure 1?1 0 . pin circuit type f-2
ks57c 0502/c0504/p0504 microcontroller address spaces 2? 1 2 address spaces program memory (rom) overview rom maps for KS57C0502/c0504 devices are mask programmable at the factory. in its standard configuration, the device's 4096 8-bit program memory has three areas that are directly addressable by the program counter (pc): ? 16-byte area for vector addresses ? 16-byte general-purpose area ? 96-byte instruction reference area ? 1920-byte general-purpose area: KS57C0502 ? 3968 -byte general-purpose area : ks57c0504 general-purpose memory two program memory areas are allocated for general-purpose use: one area is 16 bytes in size and the other is 1920 bytes (KS57C0502) or 3968 bytes (ks57c0504) . vector addresses you use the 16-byte vector address area to store the vector addresses required to execute system resets and interrupts. start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (emb) and enable register bank (erb) flags that are used to set their initial value for the corre sponding service routines. the 16-byte area can be used alternately as general-purpose rom. ref instructions locations 0020h?007fh are used as a reference area (look-up table) for 1-byte ref instructions. using ref instructions, you can reduce the byte size of instruction operands. ref can reference either one 2 -byte or two 1- byte instructions stored in the look-up table. unused look-up table addresses can be used as general-purpose rom. table 2?1. program memory address ranges rom area function address ranges area size (in bytes) vector address area 0000h?000fh 16 general-purpose program memory 0010h?001fh 16 ref instruction look-up table area 0020h?007fh 96 general-purpose program memory 0080h?0 7 ffh 0080h?0 f ffh 1920 (KS57C0502) 3968 (ks57c0504)
address spaces ks57c 0502/c0504/p0504 microcontroller 2? 2 general-purpose memory areas the 16-byte area at rom locations 0010h?001fh and the 3968 -byte area at rom locations 0080h? 0fffh are used as general-purpose program memory. you can also use vacant locations in the vector address area and ref instruction look-up table areas as gen - eral-purpose program memory. but please be careful not to overwrite live data when writing programs that use special-purpose areas of the rom. vector address area use the 16-byte vector address area of the rom to store the vector addresses for executing system resets and interrupts. the starting addresses of interrupt service routines are stored in this area, along with the enable mem - ory bank (emb) and enable register bank (erb) flag values that are needed to set emb and erb's initial values for the service routines. a 16-byte vector address is organized as follows: emb erb 0 0 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 to set up the vector address area for specific programs, you use the instruction ventn. the programming tips on the next page explain how to do this. general-purpose area (16 bytes) general-purpose area vector address area (16 bytes) instruction reference area (96 bytes) 0000h 000fh 0010h 0 01fh 0020h 007fh 0080h 0fffh general-purpose area 07ffh 0800h KS57C0502 (1,920 bytes) ks57c0504 (3,968 bytes) figure 2?1. rom structure reset intb int0 int1 ints intt0 0000h 0002h 0004h 0006h 0008h 000ah 7 6 5 4 3 2 1 0 figure 2?2. vector address map
ks57c 0502/c0504/p0504 microcontroller address spaces 2? 3 + + programming tip ? defining vectored interrupt areas the following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory: 1. when all vector interrupts are used: org 0000h ; vent0 1,0,reset ; emb ? 1, erb ? 0; jump to reset address vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address vent2 0,0,int0 ; emb ? 0, erb ? 0; jump to int0 address vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address vent4 0,0,ints ; emb ? 0, erb ? 0; jump to ints address vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to intt0 address 2. when a specific vectored interrupt such as int0, and intt0 is not used, the unused vector interrupt locations must be skipped with the assembly instruction org so that jumps will address the correct locations: org 0000h ; vent0 1,0,reset ; emb ? 1, erb ? 0; jump to reset address vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address org 0006h ; int0 interrupt not used vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address vent4 0,0,ints ; emb ? 0, erb ? 0; jump to ints address ; org 0010h ; intt0 interrupt not used 3. if an int0 interr upt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not written by a org instruction as in example 2, a cpu malfunction will occur: org 0000h ; vent0 1,0,reset ; emb ? 1, erb ? 0; jump to reset address vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int0 address vent4 0,0,ints ; emb ? 0, erb ? 0; jump to int1 address vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to ints address ; o rg 0010h ; general-purpose rom area ; in this example, when an ints interrupt is generated, the corresponding vector area is not vent4 ints, but vent5 intt0. this causes an ints interrupt to jump incorrectly to the intt0 address and causes a cpu malfunction to occur.
address spaces ks57c 0502/c0504/p0504 microcontroller 2? 4 instruction reference area using 1-byte ref instructions, you can easily reference instructions with larger byte sizes that are stored in ad dresses 0020h ?007fh of program memory. this 96-byte area is called the ref instruction reference area, or look-up table. locations in the ref look-up table may contain two one-byte instructions, a single two-byte instruction, or three-byte instructions such as a jp or call. the starting address of the instruction you are referencing must always be an even number. to reference a jp or call instruction, it must be written to the reference area in a two-byte format: for jp, this format is tjp; for call, it is tcall. in summary, there are three ways to the ref instruction: ? using the 1-byte ref instruction to execute one 2-byte or two 1-byte instructions, ? branching to any location by referencing a branch instruction stored in the look-up table, ? calling subroutines at any location by referencing a call instruction stored in the look-up table. + + programming tip ? using the ref look-up table here is one example of how to use the ref instruction look-up table: org 0020h ; jmain tjp main ; 0, main keyck btsf keyfg ; 1, keyfg check watch tcall clock ; 2, call clock inchl ld @hl,a ; 3, (hl) ? a incs hl ? ? ? abc ld ea,#00h ; 47, ea ? #00h org 0080 ; main nop nop ? ? ? ref keyck ; btsf keyfg (1-byte instruction) ref jmain ; keyfg = 1, jump to main (1-byte instruction) ref watch ; keyfg = 0, call clock (1-byte instruction) ref inchl ; ld @hl,a ; incs hl ref abc ; ld ea,#00h (1-byte instruction) ? ? ?
ks57c 0502/c0504/p0504 microcontroller address spaces 2? 5 data memory (ram) overview in its standard configuration, the 512 4 -bit data memory has five areas: ? 32 4-bit working register area ? 224 4- bit general-purpose area in bank 0 (also used as stack area) ? 256 4- bit general-purpose area in bank 1 ? 128 4-bit area for memory-mapped i/o addresses to simplify referencing, the data memory area has two memory banks ? bank 0, bank 1 and bank 15. you use the select memory bank instruction (smb) to select the bank you want to use as working data memory. data stored in ram locations are 1-, 4-, and 8-bit addressable. initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following reset . when reset signal is generated in power-down mode, the data memory contents are maintained. 000h 01fh 020h 0ffh 100h 1ffh working registers (32 x 4 bits) general-purpose registers and stack area (224 x 4 bits) general-purpose (256 x 4 bits) f80h periphral hardware registers fffh bank 0 bank 1 bank 15 ~ ~ ~ ~ figure 2?3. data memory (ram) map
address spaces ks57c 0502/c0504/p0504 microcontroller 2? 6 memory banks 0, 1 and 15 bank 0 (000h?0ffh) the lowest 32 nibbles of bank 0 (000h?01fh) are used as working registers; the next 224 nibbles (020h?0ffh) can be used both as stack area and as general-purpose data memory. use the stack area for implementing subroutine calls and returns, and for interrupt processing. bank 1 (100h ? 1ffh) this area is used as general-purpose data memory. bank 15 (f80h?fffh) the microcontroller uses bank 15 for memory-mapped peripheral i/o. fixed ram locations for each peripheral hardware address are mapped into this area. data memory addressing modes the enable memory bank (emb) flag controls the addressing mode for data memory banks 0 or 15. when the emb flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. with direct addressing, you can access locations 000h? 07fh of bank 0, bank 1 and bank 15. with indirect addressing, only bank 0 (000h?0ffh) can be accessed. when the emb flag is set to logic one, all two data memory banks can be accessed according to the current smb value. for 8-bit addressing, two 4-bit registers are addressed as a register pair. when using 8-bit instructions to ad - dress ram locations, remember to use the even-numbered register address as the instruction operand. working registers the ram working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and 3). each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable. register a is used as a 4-bit accumulator and register pair ea is an 8-bit extended accumulator. the carry flag bit can also be used as a 1-bit accumulator. register pairs wx, wl, and hl are used as address pointers for indi rect addressing. to limit the possibility of data corruption due to incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines. bit sequential carrier (bsc) the bit sequential carrier (bsc) is a 16-bit general register mapped to ram addresses fc0h?fc3h that can be manipulated by 1-, 4-, and 8-bit ram control instructions. reset clears all bit values to logic zero. you can specify addresses and bit locations sequentially using a 1-bit indirect addressing instruction. in this way, a program can process 16-bit data by moving the bit location sequentially, incrementing or decrementing the value of the l register. bsc data can also be manipulated by direct addressing. for 8-bit manipulations, you must address the upper and lower 8 bits separately.
ks57c 0502/c0504/p0504 microcontroller address spaces 2? 7 table 2?2. data memory organization and addressing addresses register areas bank emb value smb value 000h?01fh working registers 0 0, 1 0 020h?0ffh stack and general-purpose registers 100 h? 1 ffh general-purpose registers 1 1 1 f80h?fffh i/o-mapped hardware registers 15 0, 1 15 + + programming tip ? clearing data memory banks 0 and 1 clear bank 0 of the data memory area: ramclr bits emb smb 0 ld hl,#10h ld a,#0h rmcl0 ld @hl,a ; ram (010h ?0ffh) clear incs hl jr rmcl0 ;
address spaces ks57c 0502/c0504/p0504 microcontroller 2? 8 working registers working registers, mapped to ram address 000h-01fh in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. unused registers may be used as general-purpose memory. working register data can be manipulated as 1-bit units, 4- bit units or, using paired registers, as 8-bit units. 000h 0001 002h 003h 004h 005h 006h 007h 00fh 010h 017h 018h 01fh 008h data memory bank 0 a ... y a e l h x w z y a ... y working register bank 0 register bank 1 register bank 2 register bank 3 a ... y a ... y figure 2?4. working register map
ks57c 0502/c0504/p0504 microcontroller address spaces 2? 9 working register banks for addressing purposes, the working register area is divided into four register banks ? bank 0, bank 1, bank 2, and bank 3. any one of these banks can be selected as the working register bank by the register bank selection instruction ( srbn) and by setting the status of the register bank enable flag (erb). generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service rou tines. following this convention helps to prevent possible data corruption during program execution due to con tention in register bank addressing. table 2?3. working register organization and addressing erb setting srb settings selected register bank 3 2 1 0 0 0 0 x x always set to bank 0 0 0 bank 0 1 0 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 note : 'x' means don't care. paired working registers each of the register banks is subdivided into eight 4-bit registers. these registers are named y, z, w, x, h, l, e and a. you can manipulate them individually using 4-bit instructions, or as register pairs for 8-bit data manipula tion. the names of the 8-bit register pairs in each register bank are ea, hl, wx, yz and wl. registers a, l, x and z always become the lower nibble when registers are addressed as 8-bit pairs. this makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks. (msb) (lsb) (msb) (lsb) y w h e z x l a figure 2?5. register pair configuration
address spaces ks57c 0502/c0504/p0504 microcontroller 2? 10 special-purpose working registers you use register a as a 4-bit accumulator and double register ea as an 8-bit accumulator. you can use the carry flag as a 1-bit accumulator. 8-bit double registers wx, wl and hl are used as data pointers for indirect addressing. when the hl register serves as a data pointer, the instructions ldi, ldd, xchi, and xchd can make very efficient use of working reg - isters as program loop counters by letting you transfer a value and increment or decrement l register value using a single instruction. c a ea 8-bit accumulator 1-bit accumulator 4-bit accumulator figure 2?6. 1-bit, 4-bit, and 8-bit accumulator recommendation for multiple interrupt processing if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are exe - cuted in the same register bank. when the routines have executed successfully, you can restore the register con - tents from the stack to working memory using the pop instruction.
ks57c 0502/c0504/p0504 microcontroller address spaces 2? 11 + + programming tip ? selecting your working register area the following examples show the correct programming method for selecting working register area: 1. when erb = "0": vent2 1,0,int0 ; emb ? 1, erb ? 0, jump to int0 address ; int0 push sb ; push current smb, srb srb 2 ; non-essential instruction, since erb = "0" push hl ; push hl register to stack push wx ; push wx register to stack push yz ; push yz register to stack push ea ; push ea register to stack smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop ea ; pop ea register from stack pop yz ; pop yz register from stack pop wx ; pop wx register from stack pop hl ; pop hl register from stack po p sb ; pop current smb, srb iret the pop instructions execute alternately with the push instructions. if an smb ninstruction is used in an interrupt service routine, a push and pop sb instruction must be used to store and restore the current smb and srb values, as shown in example 2 below. 2. when erb = "1": vent2 1,1,int0 ; emb ? 1, erb ? 1, jump to int0 address ; int0 push sb ; store current smb, srb srb 2 ; select register bank 2 smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop sb ; restore smb, srb iret ;
address spaces ks57c 0502/c0504/p0504 microcontroller 2? 12 stack operations stack pointer (sp) the stack pointer (sp) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. the sp is mapped to ram addresses f80h -f81h, and can be read or written by 8 -bit control instruc tions. when addressing the sp, bit 0 must always remain cleared to logic zero. f80h sp3 sp2 sp1 "0" f81h sp7 sp6 sp5 sp4 there are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). a push decrements the sp and a pop increments it so that the sp always points to the top address of the last data to be written to the stack. the program counter contents and program status word are stored in the stack area prior to the execution of a call or a push instruction, or during interrupt service routines. stack operation is a lifo (last in-first out) type. the stack area is located in general-purpose data memory bank 0. during an interrupt or a subroutine, the pc value and the psw are saved to the stack area. when the routine has completed, the stack pointer is referenced to restore the pc and psw, and the next in struction is executed. the sp can address stack registers in bank 0 (addresses 000h-0ffh) regardless of the current value of the en able memory bank (emb) flag and the select memory bank (smb) flag. since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00h. this sets the first register of the stack area to 0ffh. note a subroutine call occupies six nibbles in the stack; an interrupt requires six. when subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. to do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly. although you may use general-purpose register areas for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s). + + programming tip ? initializing the stack pointer to initialize the stack pointer (sp): 1. when emb = "1": smb 15 ; select memory bank 15 ld ea,#00h ; bit 0 of accumulator a is always cleared to "0" ld sp,ea ; stack area initial address (0 ffh) ? (sp) ? 1 2. when emb = "0": ld ea,#00h ld sp,ea ; memory addressing area (00h ?7fh, f80h?fffh)
ks57c 0502/c0504/p0504 microcontroller address spaces 2? 13 push operations three kinds of push operations reference the stack pointer (sp) to write data from the source register to the stack: push in structions, call instructions, and interrupts. in each case, the sp is decremented by a number de termined by the type of push operation and then points to the next available stack location. push instructions a push instruction references the sp to write two 4-bit data nibbles from the pc to the stack. two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and another for the lower register. after the push has executed, the sp is decremented by two and points to the next available stack location. call instructions when a subroutine call is issued, the call instruction references the sp to write the pc's contents to four 4 -bit stack locations. current values for the enable memory bank (emb) flag and the enable register bank (erb) flag are also pushed to the stack. after the call has executed, the sp is decremented by six and points to the next available stack location. since six 4-bit stack locations are used per call, you may nest subroutine calls up to the number of levels permitted in the stack. interrupt routines an interrupt routine references the sp to push the contents of the pc, as well as current values for the program status word (psw) to the stack. six 4-bit stack locations are used to store this data. after the interrupt has executed, the sp is decremented by six and points to the next available stack location. during an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area. sp - 6 sp - 5 sp - 4 sp - 3 sp - 2 sp - 1 sp sp - 2 sp - 1 sp sp - 6 sp - 5 sp - 4 sp - 3 sp - 2 sp - 1 sp call (after call, sp sp - 6) emb erb 0 pc3 - pc0 pc7 - pc4 0 0 0 0 0 0 0 0 0 push (after push, sp sp - 2) lower register upper register (when int is acknowledged, sp sp - 6) interrupt 0 pc3 - pc0 pc7 - pc4 is1 is0 emb erb psw c sc2 sc1 sc0 0 0 0 pc 11-pc 8 pc 11-pc 8 figure 2?7. push-type stack operations
address spaces ks57c 0502/c0504/p0504 microcontroller 2? 14 pop operations for each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the push instruction it is the pop instruction; for call, the instruction ret or sret; for interrupts, the instruction iret. when a pop operation occurs, the sp is incremented by a number determined by the type of operation and points to the next free stack location. pop instructions a pop instruction references the sp to write data stored in two 4-bit stack locations back to the register pairs and sb register. the value for the lower 4-bit register is popped first, followed by the value for the upper 4-bit register. after the pop has exe cuted, the sp is incremented by two and points to the next free stack location. ret and sret instructions the end of a subroutine call is signaled by the return instruction, ret or sret. the ret or sret uses the sp to reference the four 4-bit stack locations used for the call and to write this data back to the pc, the emb, and erb. after the ret or sret has executed, the sp is incremented by six and points to the next free stack loca tion. iret instructions the end of an interrupt sequence is signaled by the instruction iret. iret references the sp to locate the six 4-bit stack addresses used for the interrupt and to write this data back to the pc and the psw. after the iret has executed, the sp is incremented by six and points to the next free stack location. (sp sp + 2) pop lower register upper register sp sp + 1 sp + 2 ret or sret (sp sp + 6) iret (sp sp + 6) sp sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp + 6 emb erb 0 pc3 - pc0 pc7 - pc4 0 0 0 0 0 0 0 0 0 pc11-pc8 sp sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp + 6 0 pc3 - pc0 pc7 - pc4 is1 is0 emb erb psw c sc2 sc1 sc0 0 0 0 pc11-pc8 figure 2?8. pop-type stack operations
ks57c 0502/c0504/p0504 microcontroller address spaces 2? 15 bit sequential carrier (bsc) the bit sequential carrier (bsc) is a 16-bit register that is mapped to ram addresses fc0h?fc3h. you can manipulate the bsc register using 1-, 4-, and 8-bit ram control instructions. reset clears all bsc bit values to logic zero. using the bsc, you can specify addresses and bit locations sequentially using 1-bit indirect addressing ( memb.@l). bit addressing is independent of the current emb value. in this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value of the l register. bsc data can also be manipulated using direct addressing. for 8-bit manipulations, specify the 4-bit register names bsc0 and bsc2 and manipulate the upper and lower 8 bits manipulated separately. if the values of the l register are 0h at bsc0.@l, the address and bit location assignment is fc0h.0. if the l register content is fh at bsc0.@l, the address and bit location assignment is fc3h.3. table 2?4. bsc register organization + + programming tip ? using the bsc register to output 16-bit data to use the bit sequential carrier (bsc) register to output 16-bit data (5937h) to the p3.0 pin: bits emb smb 15 ld ea,#37h ; ld bsc0,ea ; bsc0 ? a, bsc1 ? e ld ea,#59h ; ld b sc2,ea ; bsc2 ? a, bsc3 ? e smb 0 ld l,#0h ; agn ldb c,bsc0.@l ; ldb p3.0,c ; p3.0 ? c incs l jr agn ret name address bit 3 bit 2 bit 1 bit 0 bsc0 fc0h bsc0.3 bsc0.2 bsc0.1 bsc0.0 bsc1 fc1h bsc1.3 bsc1.2 bsc1.1 bsc1.0 bsc2 fc2h bsc2.3 bsc2.2 bsc2.1 bsc2.0 bsc3 fc3h bsc3.3 bsc3.2 bsc3.1 bsc3.0
address spaces ks57c 0502/c0504/p0504 microcontroller 2? 16 program counter (pc) a 1 2 -bit program counter (pc) stores addresses for instruction fetches during program execution. whenever a reset operation or an interrupt occurs, bits pc1 1 through pc0 are set to the vector address. bit pc1 2 ?pc13 is re - served to support future expansion of the device's rom size. usually, the pc is incremented by the number of bytes of the instruction being fetched. one exception is the 1-byte ref instruction which is used to reference instructions stored in the rom. program status word (psw) the program status word (psw) is an 8-bit word, mapped to ram locations fb0h?fb1h, that defines system status and program execution status and which permits an interrupted process to resume operation after an inter - rupt request has been serviced. psw values are mapped as follows: fb0h is1 is0 emb erb fb1h c sc2 sc1 sc0 the psw can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the spe - cific bit or bits being addressed. the psw can be addressed during program execution regardless of the current value of the enable memory bank (emb) flag. part or all of the psw is saved to stack prior to execution of a subroutine call or hardware interrupt. after the in terrupt has been processed, the psw values are popped from the stack back to the psw address. when a reset is generated, the emb and erb values are set according to the reset vector address, and the carry flag is left undefined (or the current value is retained). psw bits is0, is1, sc0, sc1, and sc2 are all cleared to logic zero. table 2?5. program status word bit descriptions psw bit identifier description bit addressing read/write is1, is0 interrupt status flags 1, 4 r/w emb enable memory bank flag 1 r/w erb enable register bank flag 1 r/w c carry flag 1 r/w sc2, sc1, sc0 program skip flags 8 r
ks57c 0502/c0504/p0504 microcontroller address spaces 2? 17 interrupt status flags (is0, is1) psw bits is0 and is1 contain the current interrupt execution status values. they are mapped to ram bit loca - tions fb0h.2 and fb0h.3, respectively. you can manipulate is0 and is1 flags directly using 1-bit ram control in structions by manipulating interrupt status flags in conjunction with the interrupt priority register (ipr), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. the interrupt priority control circuit determines the is0 and is1 settings in order to control multiple interrupt processing. when both interrupt status flags are set to "0", all interrupts are allowed. the priority with which interrupts are processed is then determined by the ipr. when an interrupt occurs, is0 and is1 are pushed to the stack as part of the psw and are automatically incremented to the next higher priority level. then, when the interrupt service routine ends with an iret instruc - tion, is0 and is1 values are restored to the psw. table 2?6 shows the effects of is0 and is1 flag settings. table 2?6. interrupt status flag bit settings is1 value is0 value status of currently executing process effect of is0 and is1 settings on interrupt request control 0 0 0 all interrupt requests are serviced 0 1 1 only high-priority interrupt(s) as determined in the interrupt priority register (ipr) are serviced 1 0 2 no more interrupt requests are serviced 1 1 ? not applicable; these bit settings are undefined since interrupt status flags can be addressed by write instructions, programs can exert direct control over inter rupt processing status. before interrupt status flags can be addressed, however, you must first execute a di in struction to inhibit additional interrupt routines. when the bit manipulation has been completed, execute an ei in struction to re -enable interrupt processing. + + programming tip ? setting isx flags for interrupt processing the following instruction sequence shows how to use the is0 and is1 flags to control interrupt processing: intb di ; disable interrupt bitr is1 ; is1 ? 0 bits is0 ; allow interrupts according to ipr priority level ei ; enable interrupt
address spaces ks57c 0502/c0504/p0504 microcontroller 2? 18 emb flag (emb) the enable memory bank flag emb is mapped to registers fb0h?fb1h in bank 15 of the ram. the emb flag occupies bit location 1 in register fb0h. the emb flag is used to allocate specific address locations in the ram by modifying the upper 4 bits of 12-bit data memory addresses. in this way, it controls the addressing mode for data memory banks 0 , bank 1 or 15. when the emb flag is "0", the data memory address space is restricted to bank 15 and addresses 000h?07fh of memory bank 0, regardless of the smb register contents. when the emb flag is set to "1", you can access general-purpose areas of bank 0, bank 1, and bank 15 by using the appropriate smb value. + + programming tip ? using the emb flag to select memory banks emb flag settings for memory bank selection: 1. when emb = "0": smb 0 ; non-essential instruction, since emb = "0" ld 90h,a ; (f90h) ? a, bank 15 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; non-essential instruction, since emb = "0" ld 20h,a ; (020h) ? a, bank 0 is selected ld 90h, a ; (f90h) ? a, bank 15 is selected ; 2. when emb = "1": smb 0 ; select memory bank 0 ld 90h,a ; (090h) ? a, bank 0 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; select memory bank 15 ld 20h,a ; program error, but assembler does not detect it ld 90h,a ; (f90h) ? a, bank 15 is selected ;
ks57c 0502/c0504/p0504 microcontroller address spaces 2? 19 erb flag (erb) the 1-bit register bank enable flag (erb) determines the range of addressable working register area. when the erb flag is "1", you select the working register area from register banks 0 to 3 according to the register bank se lection register (srb). when the erb flag is "0", you select register bank 0 as the working register area, regard less of the current value of the register bank selection register (srb). when an internal reset is generated, bit 6 of program memory address 0000h is written to the erb flag. this automatically initializes the flag. when a vectored interrupt is generated, bit 6 of the respective vector address table in program memory is written to the erb flag, setting the correct flag status before the interrupt service rou tine is executed. during the interrupt routine, the erb value is automatically pushed to the stack area along with the other psw bits. afterwards, it is popped back to the fb0h.0 bit location. the initial erb flag settings for each vectored inter - rupt are defined using ventn instructions. + + programming tip ? using the erb flag to select register banks erb flag settings for register bank selection: 1. when erb = "0": srb 1 ; register bank 0 is selected (since erb = "0", the ; srb is configured to bank 0) ld ea,#34h ; bank 0 ea ? #34h ld hl,ea ; bank 0 hl ? ea srb 2 ; register bank 0 is selected ld yz,ea ; bank 0 yz ? ea srb 3 ; register bank 0 is selected ld wx,ea ; bank 0 wx ? ea ; 2. when erb = "1": srb 1 ; register bank 1 is selected ld ea,#34h ; bank 1 ea ? #34h ld hl,ea ; bank 1 hl ? bank 1 ea srb 2 ; register bank 2 is selected ld yz,ea ; bank 2 yz ? bank 2 ea srb 3 ; register bank 3 is selected ld wx,ea ; bank 3 wx ? bank 3 ea ;
address spaces ks57c 0502/c0504/p0504 microcontroller 2? 20 skip condition flags (sc2, sc1, sc0) the skip condition flags sc2, sc1, and sc0 indicate the current program skip conditions and are set and reset automatically during program execution. these flags are mapped to ram bit locations fb1h.0, fb1h.1, and fb1h.2 of the psw. skip condition flags can only be addressed by 8-bit read instructions. direct manipulation of the sc2, sc1, and sc0 bits is not allowed. carry flag (c) the carry flag is mapped to bit location fb1h.3 in the psw. it is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (adc, sbc). the carry flag can also be used as a 1-bit accumulator for performing boolean operations involving bit-addressed data memory. if an overflow or borrow condition occurs when executing arithmetic instructions with carry (adc, sbc), the carry flag is set to "1". otherwise, its value is "0". when a reset occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined. the carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the psw. only the adc and sbc instructions, and the instructions listed in table 2?7, affect the carry flag. table 2?7. valid carry flag manipulation instructions operation type instructions carry flag manipulation direct manipulation scf set carry flag to "1" rcf clear carry flag to "0" (reset carry flag) ccf invert carry flag value (complement carry flag) btst c test carry and skip if c = "1" bit transfer ldb (operand) (1) ,c load carry flag value to the specified bit ldb c,(operand) (1) load contents of the specified bit to carry flag data transfer rrc a rotate right with carry flag boolean manipulation band c,(operand) (1) and the specified bit with contents of carry flag and save the result to the carry flag bor c,(operand) (1) or the specified bit with contents of carry flag and save the result to the carry flag bxor c,(operand) (1) xor the specified bit with contents of carry flag and save the result to the carry flag interrupt routine intn (2) save carry flag to stack with other psw bits return from interrupt iret restore carry flag from stack with other psw bits notes : 1. the operand has three bit addressing formats: mema.a, memb.@l, and @h + da.b. 2. intn refers to the specific interrupt being executed and is not an instruction.
ks57c 0502/c0504/p0504 microcontroller address spaces 2? 21 + + programming tip ? using the carry flag as a 1-bit accumulator 1. set the carry flag to logic one: scf ; c ? 1 ld ea,#0c3h ; ea ? #0c3h ld hl,#0aah ; hl ? #0aah adc ea,hl ; ea ? #0c3h + #0aah + #1h, c ? 1 2. logical-and bit 3 of address 3fh with p3.3 and outpu t the result to p5.0: ld h,#3h ; set the upper four bits of the address to the h register value ldb c,@h+0fh.3 ; c ? bit 3 of 3fh band c,p3.3 ; c ? c and p3.3 ldb p5.0,c ; output result from carry flag to p5.0
address spaces ks57c 0502/c0504/p0504 microcontroller 2? 22 notes
ks57c 0502/c0504/p0504 microcontroller addressing modes 3? 1 3 addressing modes overview the enable memory bank flag, emb, controls the two addressing modes for data memory. when you enable the emb flag, you can address the entire ram area. when you clear the emb flag to logic zero, the address able ram is restricted to specific areas. the emb flag works in connection with the select memory bank instruction, smb n. you will recall that the smb n instructi on is used to select ram bank 0, bank 1 or 15. the smb setting is always contained in the upper four bits of a 12-bit ram address. for this reason, both addressing modes (emb = "0" and emb = "1") apply specifically to the memory bank indicated by the smb instruction, and any restrictions to the addressable area within ban ks 0, 1 or 15. direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. in addition, there are several ram locations that can always be addressed using specific addressing methods, regardless of the current emb flag setting. here are a few things to remember about addressing data memory areas: ? when you address peripheral hardware locations in bank 15, you can use the mnemonic for the memory- mapped hardware component as the operand in place of the actual address location. ? alway s use an even-numbered ram address as the operand in 8-bit direct and indirect addressing. ? with direct addressing, use the ram address as the instruction operand; with indirect addressing, the insttruction specifies a register which contains the operand's address.
addressing modes ks57c 0502/c0504/p0504 microcontroller 3? 2 da da.b @hl @h + da.b @wx @wl mema.b memb.@l emb = 0 emb = 1 x x x 000h working registers bank 0 ( g eneral registers and stack) 01fh 020h 07fh 080h 0ffh 100h 1ffh bank 1: (general registers) ram areas addressing mode f80h fffh bank 15 (peripheral hardware registers) fb0h fbfh ff0h fc0h smb = 15 smb = 15 1. 'x' means don't care. 2. blank columns indicate ram areas that are not addressable, given the addressing method and enable memory bank (emb) flag setting shown in the column headers. notes: emb = 1 emb = 0 smb = 0 smb = 0 smb = 1 smb = 1 figure 3?1. ram address structure
ks57c 0502/c0504/p0504 microcontroller addressing modes 3? 3 emb and erb initialization values the emb and erb flag bits are set automatically by the values of the reset vector address and the interrupt vector address. when a reset is generated internally, bit 7 of program memory address 0000h is written to the emb flag, ini - tializing it automatically. when a vectored interrupt is generated, bit 7 of the respective vector address table is written to the emb. this automatically sets the emb flag status for the interrupt service routine. when the interrupt is serviced, the emb value is automatically saved to stack and then restored when the interrupt routine has com pleted. at the beginning of a program, the initial emb flag value for each vectored interrupt must be set by using vent instruction. the emb can be set or reset by bit manipulation instructions (bits, bitr) despite the current smb setting. + + programming tip ? initializing the emb and erb flags the following assembly instructions show how to initialize the emb and erb flag settings: org 0000h ; rom address assignment vent0 1,0,reset ; emb ? 1, erb ? 0, branch reset vent1 0,1,intb ; emb ? 0, erb ? 1, branch intb vent2 0,1,int0 ; emb ? 0, erb ? 1, branch int0 vent3 0,1,int1 ; emb ? 0, erb ? 1, branch int1 vent4 0,1,ints ; emb ? 0, erb ? 1, branch ints vent5 0,1,intt0 ; emb ? 0, erb ? 1, branch intt0 reset ? ? ? bitr emb
addressing modes ks57c 0502/c0504/p0504 microcontroller 3? 4 enable memory bank settings emb = "1" when you set the enable memory bank flag, emb, to logic one, you can address the data memory bank specified by the se lect memory bank (smb) value (0,1 or 15) using 1-, 4-, or 8-bit instructions. you can use both di rect and indirect addressing modes. the addressable ram areas when the emb flag is set to logic one are as follows: if smb = 0, 000h ?0ffh if smb = 1 100h ? 1 ffh if smb = 15, f80h ?fffh emb = "0" when the enable memory bank flag emb is set to logic zero, the addressable area is defined independently of the smb value, and is restricted to specific locations depending on whether a direct or indirect address mode is used. if emb = "0", the addressable area is restricted to locations 000h?07fh in bank 0 and to locations f80h? fffh in bank 15 for direct addressing. for indirect addressing, only locations 000h?0ffh in bank 0 are addressable, regardless of smb value. to address the peripheral hardware register (bank 15) using indirect addressing, the emb flag must first be set to "1" and the smb value to "15". when a reset occurs, the emb flag is set to the value contained in bit 7 of rom address 0000h. emb-independent addressing you can address several areas of the data memory at any time, despite the status of the emb flag. these ex - ceptions are described in table 3?1. table 3?1. ram addressing not affected by the emb value address addressing method affected hardware program examples 000h?0ffh 4-bit indirect addressing using wx and wl register pairs; 8-bit indirect addressing using sp not applicable ld a,@wx push pop fb0h?fbfh ff0h?fffh 1-bit direct addressing psw, iex, irqx, i/o bits emb bitr ie1 fc0h?fffh 1-bit indirect addressing using the l register bsc, i/o btst fc3h.@l band c,p3.@l
ks57c 0502/c0504/p0504 microcontroller addressing modes 3? 5 select bank register (sb) the select bank register (sb) is used to assign the memory bank and register bank. the 8-bit sb register con - sists of the 4-bit select register bank register (srb) and the 4-bit select memory bank register (smb), as shown in figure 3?2. smb 3 smb 2 smb 1 smb 0 0 0 srb 1 srb 0 srb smb sb register figure 3?2. 4-bit smb and srb values in the sb register during interrupts and subroutine calls, sb register contents can be saved to stack in 8-bit units by the push sb instruction. you later restore the value to the sb using the pop sb instruction. select register bank (srb) instruction the select register bank (srb) value specifies which register bank is to be used as a working register bank. the srb value is set by the 'srb n' instruction, where n = 0, 1, 2, 3. one of the four register banks is selected by the combination of erb flag status and the srb value that you set using the 'srb n' instruction. the current srb value is retained until another register is requested by program software. push sb and pop sb instructions are used to save and restore the contents of srb during interrupts and subroutine calls. reset clears the 4-bit srb value to logic zero. select memory bank (smb) instruction to select one of the two available data memory banks, you must execute an smb n instruction specifying the number of the memory bank you want (0, 1 or 15). for example, the instruction 'smb 1' selects bank 1 and 'smb 15' selects bank 15. you must also remember to enable the memory bank you select by the appropriate enable memory bank flag (emb) setting. the upper four bits of the 12-bit data memory address are stored in the smb register. if the smb value is not specified by software (or if a reset does not occur) the current value is retained. reset clears the 4-bit smb value to logic zero. push sb and pop sb instructions save and restore the contents of the smb register to and from the stack area during interrupts and subroutine calls.
addressing modes ks57c 0502/c0504/p0504 microcontroller 3? 6 direct and indirect addressing you can directly address 1-bit, 4-bit, and 8-bit data stored in data memory locations using a specific register or bit address as the instruction operand. in indirect addressing the instruction specifies a specfic register pair which contain the address of the operand. the ks57 instruction set supports 1-bit, 4-bit, and 8 -bit indirect addressing. for 8-bit indirect addressing, an even-numbered ram address must always be used as the instruction operand, and the address register can be hl, wx, or wl of the selected register bank. 1-bit addressing table 3?2. 1-bit direct and indirect ram addressing instruction notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h?07fh bank 0 ? da.b direct: bit is indicated by the ram address (da), memory bank selection, and specified bit number (b). 0 f80h?fffh bank15 all 1-bit ad dressable peripherals (smb = 15) 1 000h?fffh smb = 0, 1, 15 mema.b direct: bit is indicated by ad - dressable area ( mema) and bit number (b). x fb0h?fbfh ff0h?fffh bank 15 is0, is1, emb, erb, iex, irqx, pn.n memb.@l indirect: lower two bits of reg - ister l as indicated by the up - per 10 bits of ram area ( memb) and the upper two bits of register l. x fc0h?fffh bank 15 bscn.x pn.n @h + da.b indirect: bit indicated by the lower four bits of the address (da), memory bank selection, and the h register identifier. 0 000h?0ffh bank 0 ? 1 000h?fffh smb = 0, 1, 15 all 1-bit addressable pe ripherals (smb = 15) note : 'x' means don't care.
ks57c 0502/c0504/p0504 microcontroller addressing modes 3? 7 + + programming tip ? 1-bit addressing modes 1-bit direct addressing 1. if emb = "0": aflag equ 34h .3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ; non-essential instruction, since emb = "0" bits aflag ; 34h.3 ? 1 bits bflag ; f85h.3 (bmod.3) ? 1 btst cflag ; if fbah.0 (irqw) = 1, skip bits bflag ; else if fbah.0 (irqw) = 0, f85h.3 (bmod.3) ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 ; 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ; select memory bank 0 bits aflag ; 34h.3 ? 1 bits bflag ; 85h.3 ? 1 btst cflag ; if 0bah.0 = 1, skip bits bflag ; else if 0bah.0 = 0, 085h.3 ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 ;
addressing modes ks57c 0502/c0504/p0504 microcontroller 3? 8 + + programming tip ? 1-bit addressing modes (continued) 1-bit indirect addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ; non-essential instruction, since emb = "0" ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, fbah.0 (irqw) ? 1 ; 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ; select memory bank 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, 0bah.0 ? 1 ;
ks57c 0502/c0504/p0504 microcontroller addressing modes 3? 9 4-bit addressing table 3?3. 4-bit direct and indirect ram addressing instruction notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h?07fh bank 0 ? da direct: 4-bit address indicated by the ram address (da) and the memory bank selection 0 f80h?fffh bank15 all 4-bit ad dressable peripherals 1 000h?fffh smb = 0, 1, 15 (smb = 15) @hl direct: 4-bit address indi cated by the memory bank selection and register hl 0 000h?0ffh bank 0 ? 1 000h?fffh smb = 0, 15 all 4-bit addressable pe ripherals (smb = 15) @wx indirect: 4-bit address indi - cated by register wx x 000h?0ffh bank 0 ? @wl indirect: 4-bit address indi - cated by register wl x 000h?0ffh bank 0 note : 'x' means don't care. + + programming tip ? 4-bit addressing modes 4-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 8eh smb 15 ; non-essential instruction, since emb = "0" ld a,p3 ; a ? (p3) smb 0 ; non-essential instruction, since emb = "0" ld adata,a ; (046h) ? a ld bdata,a ; (f8eh) ? a ; 2. if emb = "1": adata equ 46h bdata equ 8eh smb 15 ; select memory bank 15 ld a,p3 ; a ? (p3) smb 0 ; select memory bank 0 ld adata,a ; (046h) ? a ld bdata,a ; (08 eh) ? a ;
addressing modes ks57c 0502/c0504/p0504 microcontroller 3? 10 + + programming tip ? 4-bit addressing modes (continued) 4-bit indirect addressing 1. if emb = "0", compare bank 0, locations 040h ?046h with 060h?066h: adata equ 46h bdata equ 66h smb 15 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h?046h) cpse a,@hl ; if bank 0 (060h ?066h) = a, skip sret decs l jr comp ret ; 2. if emb = "1", exchange bank 0, 040h ?046h with 060h?066h: adata equ 46h bdata equ 66h smb 0 ; select memory bank 0 ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h?046h) xchd a,@hl ; bank 0 (060h ?066h) ? a jr trans ;
ks57c 0502/c0504/p0504 microcontroller addressing modes 3? 11 8-bit addressing table 3?4. 8-bit direct and indirect ram addressing instructio n notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h?07fh bank 0 ? da direct: 8-bit address indicated by the ram address ( da = even number ) and memory bank selection 0 f80h?fffh bank15 all 8-bit addressable pe ripherals (smb = 15) 1 000h?fffh smb = 0, 1, 15 @hl indirect: the 8-bit address indi - cated by the memory bank selection and register hl; (the 4 -bit l register value must be an even number) 0 000h?0ffh bank 0 ? 1 000h?fffh smb = 0, 1, 15 all 8-bit ad dressable pe ripherals (smb = 15) + + programming tip ? 8-bit addressing modes 8-bit direct addressing: 1. if emb = " 0": adata equ 46h bdata equ 8eh smb 15 ; non-essential instruction, since emb = "0" ld ea,p4 ; e ? (p5), a ? (p4) ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (f8eh) ? a, (f8fh) ? e ; 2. if emb = "1": adata equ 46h bdata equ 8eh smb 15 ; select memory bank 15 ld ea,p4 ; e ? (p5), a ? (p4) smb 0 ; select memory bank 0 ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (08eh) ? a, (08fh) ? e ;
addressing modes ks57c 0502/c0504/p0504 microcontroller 3? 12 + + programming tip ? 8-bit addressing modes (continued) 8-bit indirect addressing 1. if emb = "0": adata equ 8eh ld hl,#adata ld ea,@hl ; a ? (08eh), e ? (08fh) ; 2. if emb = "1": adata equ 46h smb 0 ld hl,#adata ld ea,@hl ; a ? (046h), e ? (047h) ;
ks57c 0502/c0504/p0504 microcontroller memory map 4? 1 4 memory map overview to support program control of peripheral hardware, i/o addresses for peripherals are memory-mapped to bank 15 of the ram. memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. access to bank 15 is controlled by the select memory bank (smb) instruction and by the enable memory bank flag (emb) setting.if the emb flag is "0", bank 15 can be addressed using direct addressing, regardless of the current smb value. you can use 1-bit direct and indirect addressing, however, for specific locations in bank 15, regardless of the current emb value. i/o map for hardware registers table 4?1 contains detailed information about i/o mapping for peripheral hardware in bank 15 (register loca - tions f80h?fffh). use the i/o map as a quick-reference source when writing application programs. the i/o map gives you the following information: ? register address ? register name (mnemonic for program addressing) ? bit values (both addressable and non- manipulable) ? read-only, write-only, or read and write addressability ? 1-bit, 4-bit, or 8-bit data manipulation characteristics
memory map ks57c 0502/c0504/p0504 microcontroller 4? 2 table 4?1. i/o map for memory bank 15 memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit f80h sp .3 .2 .1 "0" r/w no no yes f81h .7 .6 .5 .4 ? ? f85h bmod .3 .2 .1 .0 w .3 yes no f86h bcnt r no no yes f87h f88h wmod "0" .2 .1 "0" (1) w no no yes f89h .7 "0" .5 .4 ? ? f90h tmod0 .3 .2 "0" "0" w .3 no yes f91h "0" .6 .5 .4 f92h "0" toe0 "0" "0" r/w yes yes no f93h f94h tcnt0 r no no yes f95h f96h tref0 w no no yes f97h f9 8 h wdmod .3 .2 .1 .0 w no no yes f99 h .7 .6 .5 .4 f9a h wdtcf .3 "0" "0" "0" w yes no no ? ? fb0h psw is1 is0 emb erb r/w yes yes yes fb1h c (2) sc2 sc1 sc0 r no no fb2h ipr ime .2 .1 .0 w ime yes no fb3h pcon .3 .2 .1 .0 w no yes no fb4h imod0 .3 "0" .1 .0 w no yes no fb5h imod1 "0" "0" "0" .0 w no yes no fb6h imodk "0" .2 .1 .0 w n o yes no fb7h
ks57c 0502/c0504/p0504 microcontroller memory map 4? 3 table 4?1. i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fb8h "0" "0" ieb irqb r/w yes yes no fb9h fbah "0" "0" iew irqw r/w yes yes no fbbh fbch "0" "0" iet0 irqt0 fbdh "0" "0" ies irqs r/w yes yes no fbeh ie1 irq1 ie0 irq0 fbfh "0" "0" iek irqk fc0h bsc0 r/w yes yes yes fc1h bsc1 r/w yes fc2h bsc2 r/w yes yes fc3h bsc3 r/w yes ? ? fd0h clmod .3 "0" .1 .0 w no yes no ? ? fd4h cmpreg r no yes no fd5h fd6h cmod .3 .2 .1 .0 r/w no no yes fd7h .7 .6 .5 "0" ? ? fd a h pne pne4.3 pne4.2 pne4.1 pne4.0 w no no yes fdb h pne5.3 pne5.2 pne5.1 pne5.0 fdch pumod .3 "0" .1 .0 w no no yes fddh "0" .6 .5 .4 fdeh fdfh fe0h smod .3 .2 .1 .0 w .3 no yes fe1h .7 .6 .5 "0"
memory map ks57c 0502/c0504/p0504 microcontroller 4? 4 table 4?1. i/o map for memory bank 15 (concluded) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fe2h p2mod .3 .2 .1 .0 w no yes no fe3h fe4h sbuf r/w no no yes fe5h fe6h fe7h fe8h pmg1 "0" pm0.2 pm0.1 pm0.0 w no no yes fe9h "0" pm3.2 pm3.1 pm3.0 feah pmg2 pm4.3 pm4.2 pm4.1 pm4.0 w no no yes febh "0" "0" "0" "0" fech pmg3 pm5.3 pm5.2 pm5.1 pm5.0 w no no yes fedh pm6.3 pm6.2 pm6.1 pm6.0 feeh fefh ff0h port 0 ? .2 .1 .0 r/w yes yes no ff1h port 1 ? ? .1 .0 r no ff2h port 2 .3 .2 .1 .0 r no ff3h port 3 ? .2 .1 .0 r/w no ff4h port 4 .3 .2 .1 .0 r/w yes ff5h port 5 .3 / .7 .2 / .6 .1 / .5 .0 / .4 r/w ff6h port 6 .3 .2 .1 .0 r/w no ? ? ? fffh notes: 1. bit 0 in the wmod register must be set to logic "0". 2. the carry flag can be read or written by specific bit manipulation instructions only.
ks57c 0502/c0504/p0504 microcontroller memory map 4? 5 register descriptions in this section, register descriptions are presented in a consistent format to familiarize you with the memory- mapped i/o locations in bank 15 of the ram. figure 4?1 describes features of the register description format. register descriptions are arranged in alphabetical order. counter registers, buffer registers, and reference registers, as well as the stack pointer and port i/o latches, are not included in these descriptions. this section can be used as a quick-reference source when writing application programs. more detailed information about each of these registers is included in part ii of this manual, "hardware descriptions," in the context of the corresponding peripheral hardware module descriptions.
memory map ks57c 0502/c0504/p0504 microcontroller 4? 6 ipr ? interrupt priority register fb2h bit identifier reset value read/write bit addressing ime .2 ? .0 global interrupt enable bit interrupt priority assignment bits w w w w 1/4 0 0 0 0 3 2 1 0 ime .2 .1 .0 0 1 disable interrupt processing globally enable interrupt processing globally process i n tb interrupts only process int0 interrupts only process int1 interrupts only process intt interrupts only register id register name register location in ram bank 15 bit number in msb to lsb order bit identifier used for bit addressing bit value immediately following a reset type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) r w r/w '?' = = = = read-only write-only read/write not used bit identifiers used for bit addressing description of the effect of specific bit settin g s name of individual bit or related bits 4 4 4 0 0 0 1 1 process all interrupt requests at low priority 0 1 0 1 0 0 1 0 1 1 figure 4?1. register description format
ks57c 0502/c0504/p0504 microcontroller memory map 4? 7 b mod ? basic timer mode register f85h bit 3 2 1 0 identifier .3 .2 .1 .0 reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 bmod.3 basic timer restart bit 1 restart basic timer, then clear irqb flag, bcnt and bmod.3 to logic zero bmod.2 ? .0 input clock frequency and signal stabilization interval control bits 0 0 0 input clock frequency: signal stabilization interval: fx / 2 12 (1.02 khz) 2 20 / fx (250 ms) 0 1 1 input clock frequency: signal stabilization interval: fx / 2 9 (8.18 khz) 2 17 / fx (31.3 ms) 1 0 1 input clock frequency: signal stabilization interval: fx / 2 7 (32.7 khz) 2 15 / fx (7.82 ms) 1 1 1 input clock frequency: signal stabilization interval: fx / 2 5 (131 khz) 2 13 / fx (1.95 ms) notes : 1. signal stabilization interval is the time required to stabilize clock signal oscillation after stop mode is terminated by an interrupt. 2. when a reset occurs, the oscillation stabilization time is 31.3 ms at 4.19 mhz. 3. ' fx' is the system clock rate given a clock frequency of 4.19 mhz.
memory map ks57c 0502/c0504/p0504 microcontroller 4? 8 cmod ? comparator mode register fd7h, fd6h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 "0" .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w bit addressing 8 8 8 8 8 8 8 8 cmod.7 comparator enable/disable bit 1 comparator operation enable 0 comparator operation disable cmod.5 external/internal reference selection bit 1 external reference at cin3, cin0?2: analog input 0 internal reference, cin0?3: analog input cmod.6 conversion time control bit 1 4 2 4 / fx, 15.2 s @4.19 mhz 0 4 2 7 / fx, 121.6 s @4.19 mhz cmod.4 bit 4 0 always logic zero cmod.3 ? .0 reference voltage selection bits selected v ref v dd (n + 0.5) 16 , n = 0 to 15
ks57c 0502/c0504/p0504 microcontroller memory map 4? 9 clmod ? clock output mode register fd0h bit 3 2 1 0 identifier .3 "0" .1 .0 reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 clmod.3 enable/disable clock output control bit 0 disable clock output 1 enable clock output clmod.2 bit 2 0 always logic zero clmod.1 ? .0 clock source and frequency selection control bits 0 0 select cpu clock source fx/4, fx/8, or fx/64 (1.05 mhz, 524 khz, or 65.6 khz) 0 1 select system clock fx/8 (524 khz) 1 0 select system clock fx/16 (262 khz) 1 1 select system clock fx/64 (65.5 khz) note : fx' is the system clock given a clock frequency of 4.19 mhz.
memory map ks57c 0502/c0504/p0504 microcontroller 4? 10 ie0, 1, irq0, 1 ? int0, 1 interrupt enable/request flags fbeh bit 3 2 1 0 identifier ie1 irq1 ie0 irq0 reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 ie1 int1 interrupt enable flag 0 disable interrupt requests at the int1 pin 1 enable interrupt requests at the int1 pin irq1 int1 interrupt request flag ? generate int1 interrupt (bit is set and cleared by hardware when rising or falling edge detected at int1 pin.) ie0 int0 interrupt enable flag 0 disable interrupt requests at the int0 pin 1 enable interrupt requests at the int0 pin irq0 int0 interrupt request flag ? generate int0 interrupt (bit is set and cleared by hardware when rising or falling edge detected at int0 pin.)
ks57c 0502/c0504/p0504 microcontroller memory map 4? 11 iek, irqk ? key interrupt enable/request register fbfh bit 3 2 1 0 identifier 0 0 iek irqk reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 ? .2 bits 3?2 0 always logic zero iek key interrupt request enable flag 0 disable intk interrupt requests at the ks0?ks2 pins 1 enable intk interrupt requests at the ks0?ks2 pin irqk key interrupt request flag ? generate intk interrupt. (this bit is set when falling edge detected any at one of the ks0?ks2 pins. intk is a quasi-interrupt and irqk must be cleared by software.)
memory map ks57c 0502/c0504/p0504 microcontroller 4? 12 ieb, irqb ? intb interrupt enable/request flags fb8h bit 3 2 1 0 identifier 0 0 ieb irqb reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 ? . 2 bits 3?2 0 always logic zero ieb intb interrupt enable flag 0 disable intb interrupt requests 1 enable intb interrupt requests irqb intb interrupt request flag ? generate intb interrupt (bit is set and cleared automatically by hardware when reference interval signal received from basic timer.)
ks57c 0502/c0504/p0504 microcontroller memory map 4? 13 ies, irqs ? ints interrupt enable/request flags fbdh bit 3 2 1 0 identifier 0 0 ies irqs reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 ? .2 bits 3?2 0 always logic zero ies ints interrupt enable flag 0 disable ints interrupt requests 1 enable ints interrupt requests irqs ints interrupt request flag ? generate ints interrupt (bit is set and cleared automatically by hardware when transmit or receive operation is completed.)
memory map ks57c 0502/c0504/p0504 microcontroller 4? 14 iet0, irqt0 ? intt0 interrupt enable/request flags fbch bit 3 2 1 0 identifier 0 0 iet0 irqt0 reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 ? .2 bits 3?2 0 always logic zero iet0 intt0 interrupt enable flag 0 disable intt0 interrupt requests 1 enable intt0 interrupt requests irqt0 intt0 interrupt request flag ? generate intt0 interrupt (bit is set and cleared automatically by hardware when contents of tcnt0 and tref0 registers match.)
ks57c 0502/c0504/p0504 microcontroller memory map 4? 15 iew, irqw ? intw interrupt enable/request flags fbah bit 3 2 1 0 identifier 0 0 iew irqw reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 ? .2 bits 3?2 0 always logic zero iew intw interrupt enable flag 0 disable intw interrupt requests 1 enable intw interrupt requests irqw intw interrupt request flag ? generate intw interrupt (bit is set when timer interval = 0.5 s or 3.19 ms) note : intw is a quasi-interrupt and its request flag must be cleared by software.
memory map ks57c 0502/c0504/p0504 microcontroller 4? 16 imod0 ? external interrupt 0 (int0) mode register fb4h bit 3 2 1 0 identifier .3 "0" .1 .0 reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod0.3 interrupt sampling clock selection bit 0 select cpu clock as a sampling clock 1 select sampling clock frequency of the system clock ( fx)/64 imod0.2 bit 2 0 always logic zero imod0.1 ? .0 external interrupt mode control bits 0 0 interrupt requests are triggered by a rising signal edge 0 1 interrupt requests are triggered by a falling signal edge 1 0 interrupt requests are triggered by both rising and falling signal edges 1 1 interrupt request flag (irq0) cannot be set to logic one
ks57c 0502/c0504/p0504 microcontroller memory map 4? 17 imod1 ? external interrupt 1 (int1) mode register fb5h bit 3 2 1 0 identifier "0" "0" "0" .0 reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod1.3 ? .1 bits 3?1 0 always logic zero imod1.0 external interrupt 1 edge detection control bit 0 rising edge detection 1 falling edge detection
memory map ks57c 0502/c0504/p0504 microcontroller 4? 18 imodk ? key interrupt mode register fb6h bit 3 2 1 0 identifier "0" .2 .1 .0 reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imodk.3 bits 3 0 always logic zero imodk.2 ? .0 key interrupt edge detection selection bit 0 0 0 interrupt request is disabled 0 0 1 interrupt request at ks0 triggered by falling edge 0 1 0 interrupt request at ks1 triggered by falling edge 0 1 1 interrupt request at ks0?ks1 triggered by falling edge 1 0 0 interrupt request at ks2 triggered by falling edge 1 0 1 interrupt request at ks0, ks2 triggered by falling edge 1 1 0 interrupt request at ks1.?ks2 triggered by falling edge 1 1 1 interrupt request at ks0?ks2 triggered by falling edge
ks57c 0502/c0504/p0504 microcontroller memory map 4? 19 ipr ? interrupt priority register fb2h bit 3 2 1 0 identifier ime .2 .1 .0 reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 ime interrupt master enable bit 0 inhibit all interrupt processing 1 enable processing for all interrupt service requests ipr.2 ? .0 interrupt priority assignment bits 0 0 0 process all interrupt requests at low priority 0 0 1 process intb interrupt only 0 1 0 process int0 interrupts only 0 1 1 process int1 interrupts only 1 0 0 process ints interrupts only 1 0 1 process intt0 interrupts only
memory map ks57c 0502/c0504/p0504 microcontroller 4? 20 pcon ? clock power control register fb3h bit 3 2 1 0 identifier .3 .2 .1 .0 reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 pcon.3 ? .2 cpu operating mode control bits 0 0 enable normal cpu operating mode 0 1 initiate idle power-down mode 1 0 initiate stop power-down mode pcon.1 ? .0 cpu clock frequency selection bits 0 0 select ( fx)/64 1 0 select fx/8 1 1 select fx/4 * fx = system clock
ks57c 0502/c0504/p0504 microcontroller memory map 4? 21 pmg1 ? port i/o mode flags (group 1: ports 0, 3) fe9h, fe8h bit 7 6 5 4 3 2 1 0 identifier "0" pm3.2 pm3.1 pm3.0 "0" pm0.2 pm0.1 pm0.0 reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 bit 7 0 always logic zero pm3.2 p3.2 i/o mode selection flag 0 set p3.2 to input mode 1 set p3.2 to output mode pm3.1 p3.1 i/o mode selection flag 0 set p3.1 to input mode 1 set p3.1 to output mode pm3.0 p3.0 i/o mode selection flag 0 set p3.0 to input mode 1 set p3.0 to output mode .4 bit 4 0 always logic zero pm0.2 p0.2 i/o mode selection flag 0 set p0.2 to input mode 1 set p0.2 to output mode pm0.1 p0.1 i/o mode selection flag 0 set p0.1 to input mode 1 set p0.1 to output mode pm0.0 p0.0 i/o mode selection flag 0 set p0.0 to input mode 1 set p0.0 to output mode
memory map ks57c 0502/c0504/p0504 microcontroller 4? 22 pmg2 ? port i/o mode flags (group 2: port 4) febh, feah bit 7 6 5 4 3 2 1 0 identifier "0" "0" "0" "0" pm4.3 pm4.2 pm4.1 pm4.0 reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 bit 7 0 always logic zero .6 bit 6 0 always logic zero .5 bit 5 0 always logic zero .4 bit 4 0 always logic zero pm4.3 p4.3 i/o mode selection flag 0 set p4.3 to input mode 1 set p4.3 to output mode pm4.2 p4.2 i/o mode selection flag 0 set p4.2 to input mode 1 set p4.2 to output mode pm4.1 p4.1 i/o mode selection flag 0 set p4.1 to input mode 1 set p4.1 to output mode pm4.0 p4.0 i/o mode selection flag 0 set p4.0 to input mode 1 set p4.0 to output mode
ks57c 0502/c0504/p0504 microcontroller memory map 4? 23 pmg3 ? port i/o mode flags (group 3: port 5, 6) fedh, fech bit 7 6 5 4 3 2 1 0 identifier pm6.3 pm6.2 pm6.1 pm6.0 pm5.3 pm5.2 pm5.1 pm5.0 reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm6.3 p6.3 i/o mode selection flag 0 set p6.3 to input mode 1 set p6.3 to output mode pm6.2 p6.2 i/o mode selection flag 0 set p6.2 to input mode 1 set p6.2 to output mode pm6.1 p6.1 i/o mode selection flag 0 set p6.1 to input mode 1 set p6.1 to output mode pm6.0 p6.0 i/o mode selection flag 0 set p6.0 to input mode 1 set p6.0 to output mode pm5.3 p5.3 i/o mode selection flag 0 set p5.3 to input mode 1 set p5.3 to output mode pm5.2 p5.2 i/o mode selection flag 0 set p5.2 to input mode 1 set p5.2 to output mode pm5.1 p5.1 i/o mode selection flag 0 set p5.1 to input mode 1 set p5.1 to output mode pm5.0 p5.0 i/o mode selection flag 0 set p5.0 to input mode 1 set p5.0 to output mode
memory map ks57c 0502/c0504/p0504 microcontroller 4? 24 pne ? n-channel open-drain enable register f da h bit 7 6 5 4 3 2 1 0 identifier pne5 .3 pne5 .2 pne5 .1 pne5 .0 pne4 .3 pne4 .2 pne4 .1 pne4 .0 reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 p5 .3 n-channel open-drain enable bit 0 set p5 .3 open-drain disabled 1 set p 5 .3 open-drain enabled .6 p5 . 2 n-channel open-drain enable bit 0 set p5.2 open-drain disabled 1 set p 5.2 open-drain enabled .5 p5.1 n-channel open-drain enable bit 0 set p5.1 open-drain disabled 1 set p 5.1 open-drain enabled .4 p5.0 n-channel open-drain enable bit 0 set p5.0 open-drain disabled 1 set p 5.0 open-drain enabled .3 p4 .3 n-channel open-drain enable bit 0 set p4 .3 open-drain disabled 1 set p 4 .3 open-drain enabled .2 p4.2 n-channel open-drain enable bit 0 set p4.2 open-drain disabled 1 set p 4.2 open-drain enabled .1 p4.1 n-channel open-drain enable bit 0 set p4.1 open-drain disabled 1 set p 4.1 open-drain enabled .0 p4.0 n-channel open-drain enable bit 0 set p4.0 open-drain disabled 1 set p 4.0 open-drain enabled
ks57c 0502/c0504/p0504 microcontroller memory map 4? 25 psw ? program status word fb1h, fb0h bit 7 6 5 4 3 2 1 0 identifier c sc2 sc1 sc0 is1 is0 emb erb reset value (note 1) 0 0 0 0 0 0 0 read/write r/w r r r r/w r/w r/w r/w bit addressing (note 2) 8 8 8 1/4 1/4 1 1 c carry flag 0 no overflow or borrow condition exists 1 an overflow or borrow condition does exist sc2 ? sc0 skip condition flags 0 no skip condition exists; no direct manipulation of these bits is allowed 1 a skip condition exists; no direct manipulation of these bits is allowed is1, is0 interrupt status flags 0 0 service all interrupt requests 0 1 service only the high-priority interrupt(s) as determined in the interrupt priority register (ipr) 1 0 do not service any more interrupt requests 1 1 undefined emb enable data memory bank flag 0 restrict program access to data memory to bank 15 (f80h?fffh) and to the locations 000h?07fh in the bank 0 only 1 enable full access to data memory banks 0, 1, and 15 erb enable register bank flag 0 select register bank 0 as working register area 1 select register banks 0, 1, 2, or 3 as working register area in accordance with the select register bank (srb) instruction operand notes : 1. the value of the carry flag after a reset occurs during normal operation is undefined. if a reset occurs during power-down mode (idle or stop), the current value of the carry flag is retained. 2. the carry flag can only be addressed by a specific set of 1-bit manipulation instructions. see section 2 for detailed information.
memory map ks57c 0502/c0504/p0504 microcontroller 4? 26 p2mod ? port 2 mode register fe2h bit 3 2 1 0 identifier .3 .2 .1 .0 reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 p2mod.3 p2.3 analog/digital selection bit 0 configure p2.3 as an analog input pin 1 configure p2.3 as an digital input pin p2mod.2 p2.2 analog/digital selection bit 0 configure p2.2 as an analog input pin 1 configure p2.2 as an digital input pin p2mod.1 p2.1 analog/digital selection bit 0 configure p2.1 as an analog input pin 1 configure p2.1 as an digital input pin p2mod.0 p2.0 analog/digital selection bit 0 configure p2.0 as an analog input pin 1 configure p2.0 as an digital input pin
ks57c 0502/c0504/p0504 microcontroller memory map 4? 27 pumod ? pull-up register mode register f dc h, f dd h bit 7 6 5 4 3 2 1 0 identifier "0" .6 .5 .4 .3 "0" .1 .0 reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 bit 7 0 always cleared to logic zero .6 connect/disconnect port 6 pull-up resistor control bit 0 disconnect port 6 pull-up resistor 1 connect port 6 pull-up resistor .5 connect/disconnect port 5 pull-up resistor control bit 0 disconnect port 5 pull-up resistor 1 connect port 5 pull-up resistor .4 connect/disconnect port 4 pull-up resistor control bit 0 disconnect port 4 pull-up resistor 1 connect port 4 pull-up resistor .3 connect/disconnect port 3 pull-up resistor control bit 0 disconnect port 3 pull-up resistor 1 connect port 3 pull-up resistor .2 bit 2 0 always cleared to logic zero .1 connect/disconnect port 1 pull-up resistor control bit 0 disconnect port 1 pull-up resistor 1 connect port 1 pull-up resistor .0 connect/disconnect port 0 pull-up resistor control bit 0 disconnect port 0 pull-up resistor 1 connect port 0 pull-up resistor
memory map ks57c 0502/c0504/p0504 microcontroller 4? 28 smod ? serial i/o mode register fe1h, fe0h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 "0" .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write w w w w r/w w w w bit addressing 8 8 8 8 1 8 8 8 smod.7 ? .5 serial i/o clock selection and sbuf r/w status control bits 0 0 0 use an external clock at the sck pin; enable sbuf when sio operation is halted or when sck goes high 0 0 1 use the tol0 clock from timer/counter 0; enable sbuf when sio operation is halted or when sck goes high 0 1 x use the selected cpu clock (fx/4, 8, or 64; ' fx' is the system clock) then, enable sbuf read/write operation. 'x' means 'don't care.' 1 0 0 4.09 khz clock (fx/2 10 ) 1 1 1 262 khz clock (fx/2 4 ); note: you cannot select a fx/2 4 clock fre - quency if you have selected a cpu clock of fx/64 note: all khz frequency ratings assume a system clock of 4.19 mhz. smod.4 bit 4 0 always logic zero smod.3 initiate serial i/o operation bit 1 clear irqs flag and 3-bit clock counter to logic zero; then initiate serial trans - mission. when sio transmission starts, this bit is cleared by hardware to logic zero smod.2 enable/disable sio data shifter and clock counter bit 0 disable the data shifter and clock counter; retain contents of irqs flag when serial transmission is completed 1 enable the data shifter and clock counter; the irqs flag is set to logic one when serial transmission is completed smod.1 serial i/o transmission mode selection bit 0 receive-only mode 1 transmit-and-receive mode smod.0 lsb/msb transmission mode selection bit 0 transmit the most significant bit (msb) first 1 transmit the least significant bit (lsb) first
ks57c 0502/c0504/p0504 microcontroller memory map 4? 29 tmod0 ? timer/counter 0 mode register f91h, f90h bit 3 2 1 0 3 2 1 0 identifier "0" .6 .5 .4 .3 .2 "0" "0" reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1 8 8 8 .7 bit 7 0 always logic zero .6 ? .4 timer/counter 0 input clock selection bits 0 0 0 external clock input at tcl0 pin on rising edge 0 0 1 external clock input at tcl0 pin on falling edge 1 0 0 internal system clock ( fx) of 4.19 mhz / 2 10 (4.09 khz) 1 0 1 selected clock: fx/2 6 (65.5 khz) 1 1 0 selected clock: fx/2 4 (262 khz) 1 1 1 selected clock: fx (4.19 mhz) .3 clear counter and resume counting control bit 1 clear tcnt0, irqt0, and tol0 and resume counting immediately. (this bit is cleared automatically when counting starts.) .2 enable/disable timer/counter 0 bit 0 disable timer/counter 0; retain tcnt0 contents 1 enable timer/counter 0 .1 bit 1 0 always logic zero .0 bit 0 0 always logic zero note : system clock frequency ( fx) is assumed to be 4.19 mhz.
memory map ks57c 0502/c0504/p0504 microcontroller 4? 30 toe0 ? timer output enable flag f92 h bit 3 2 1 0 identifier 0 toe0 0 0 reset value 0 0 0 0 read/write r/w r/w r/w w bit addressing 1/4 1/4 1/4 1/4 .3 bit 3 0 always logic zero toe0 timer/counter 0 output enable flag 0 disable timer/counter 0 output to the tclo0 pin 1 enable timer/counter 0 output to the tclo0 pin .1 bit 1 0 always logic zero .0 bit 0 0 always logic zero
ks57c 0502/c0504/p0504 microcontroller memory map 4? 31 wdmod ? watch-dog timer mode register f 98 h, f 99 h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 1 0 1 0 0 1 0 1 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 - .0 watch-dog timer enable/disable control 5ah disable watch-dog timer function any other value enable watch-dog timer function wdtcf ? watch-dog timer flag f9a h bit 3 2 1 0 identifier wdtcf ?0? ?0? ?0? reset value 0 0 0 0 read/write w ? ? ? bit addressing 1 ? ? ? .3 watch-dog timer?s counter clear bit 1 clear and restart the watch-dog timer?s counter note : instruction that clear the watch-dog timer (?bits wdtcf?) should be executed at proper points in a program within a given period. if not executed within a given period and watch-dog timer overflows, reset signal is generated and system is restarted with reset status.
memory map ks57c 0502/c0504/p0504 microcontroller 4? 32 wmod ? watch timer mode register f89h, f88h bit 7 6 5 4 3 2 1 0 identifier .7 "0" .5 .4 "0" .2 .1 "0" reset value 0 0 0 0 0 0 0 0 read/write w w w w r w w w bit addressing 8 8 8 8 1 8 8 8 wmod.7 enable/disable buzzer output bit 0 disable buzzer (buz) signal output 1 enable buzzer (buz) signal output wmod.6 bit 6 0 always logic zero wmod.5 ? .4 output buzzer frequency selection bits 0 0 2 khz buzzer (buz) signal output 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output wmod.3 bit 3 0 always logic zero wmod.2 enable/disable watch timer bit 0 disable watch timer and clear frequency dividing circuits 1 enable watch timer wmod.1 watch timer speed control bit 0 normal speed; set irqw to 0.5 seconds 1 high-speed operation; set irqw to 3.91 ms wmod.0 bit 0 0 always logic zero (must be set to zero)
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 1 5 sam47 instruction set overview the ks57 instruction set includes 1-bit, 4-bit, and 8-bit instructions for data manipulation, logical and arithmetic operations, program control, and cpu control. i/o instructions for peripheral hardware devices are flexible and easy to use. you can substitute symbolic hardware names as the instruction operand in place of the actual ad - dress. other important features of the ks57 instruction set include: ? 1-byte referencing of long instructions (ref instruction) ? redundant instruction reduction (string effect) ? skip feature for adc and sbc instructions instruction operands conform to the operand format defined for each instruction. several instructions have mul - tiple operand formats. predefined values or labels can be used as instruction operands when addressing immediate data. many of the symbols for specific registers and flags may also be substituted as labels for operations such da, mema, memb, b, and so on. using instruction labels can greatly simplify program writing and debugging tasks. instruction set features in this section, the following ks57 instruction set features are described in detail: ? instruction reference area ? instruction redundancy reduction ? flexible bit manipulation ? adc and sbc instruction skip condition instruction reference area using the 1-byte ref ( reference) instruction, you can reference instructions stored in addresses 0020h?007fh of program memory (the ref instruction look-up table). the location referenced by ref may contain either two 1-byte instructions or a single 2-byte instruction. the starting address of the instruction being referenced must always be an even number. 3-byte instructions such as jp or call may also be referenced using ref. to reference these 3-byte instructions, the 2-byte pseudo commands tjp and tcall must be written to the reference area instead of the normal jp or call instruction. the pc is not incremented when a ref instruction is executed. after it executes, the program's instruction ex - ecution sequence resumes at the address immediately following the ref instruction. by using ref instructions to execute instructions larger than one byte, as well as branches and subroutines, you can reduce the total number of program steps. to summarize, the ref instruction can be used in three ways: ? using the 1-byte ref instruction to execute one 2-byte or two 1-byte instructions; ? branching to any location by referencing a branch address that is stored in the look-up table; ? calling subroutines at any location by referencing a call address that is stored in the look-up table.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 2 instruction reference area (continued) if necessary, a ref instruction can be circumvented by means of a skip operation prior to the ref in the exe - cution sequence. in addition, the instruction immediately following a ref can also be skipped by using an ap - propriate reference instruction or instructions. two-byte instructions that you can reference using a ref instruction are limited to instructions with an execu tion time of two machine cycles. (an exception to this rule is xch a,da. ) in addition, when you use ref to ref - erence two 1-byte instructions stored in the reference area, you must meet specific conditions for the first and second 1-byte instruction. these combinations are described in table 5?1. table 5?1. valid 1-byte instruction combinations for ref look-ups note : if the msb value of the first one-byte instruction is "0", the instruction cannot be referenced by a ref instruction. first 1-byte instruction second 1-byte instruction instruction operand instruction operand ld a,@hl incs l ld @hl,a decs l incs h decs h incs hl ld a,@wx incs x decs x incs w decs w incs wx ld a,@wl incs l decs l incs w decs w
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 3 reducing instruction redundancy when redundant instructions such as ld a,#im and ld ea,#imm are used consecutively in a program se quence, only the first instruction is executed. the redundant instructions which follow are ignored, that is, they are handled like a nop instruction. when ld hl,#imm instructions are used consecutively, redundant instructions are also ignored. in the following example, only the 'ld a, # im' instruction will be executed. the 8-bit load instruction which fol lows it is interpreted as redundant and is ignored: ld a,#im ; load 4-bit immediate data (# im) to accumulator ld ea,#imm ; load 8-bit immediate data (# imm) to extended accumulator in this example, the statements 'ld a,#2h' and 'ld a,#3h' are ignored: bitr emb ld a,#1h ; execute instruction ld a,#2h ; ignore, redundant instruction ld a,#3h ; ignore, redundant instruction ld 23h,a ; execute instruction, 023h ? #1h if consecutive ld hl, # imm instructions (load 8-bit immediate data to the 8-bit memory pointer pair, hl) are de - tected, only the first ld is executed and the lds which immediately follow are ignored. for example, ld hl,#10h ; hl ? 10h ld hl,#20h ; ignore, redundant instruction ld a,#3h ; a ? 3h ld ea,#35h ; ignore, redundant instruction ld @hl,a ; (10h) ? 3h if an instruction reference with a ref instruction has a redundancy effect, the following conditions apply: ? if the instruction preceding the ref has a redundancy effect, this effect is cancelled and the referenced in - struction is not skipped. ? if the instruction following the ref has a redundancy effect, the instruction following the ref is skipped. + + p rogramming tip ? example of the instruction redundancy effect org 0020h abc ld ea,#30h ; stored in ref instruction reference area org 0080h ? ? ? ld ea,#40h ; redundancy effect is encou ntered ref abc ; no skip (ea ? #30h) ? ? ? ref abc ; ea ? #30h ld ea,#50h ; skip
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 4 flexible bit manipulation in addition to normal bit manipulation instructions like set and clear, the ks57 instruction set can also perform bit tests, bit transfers, and bit boolean operations. bits can also be addressed and manipulated by special bit ad - dressing modes. three types of bit addressing are supported: ? mema.b ? memb.@l ? @ h+da.b the parameters of these bit addressing modes are described in more detail in table 5?2. table 5?2. bit addressing modes and parameters addressing mode addressable peripherals address range mema.b erb, emb, is1, is0, iex, irqx fb0h?fbfh ports 0?6 ff0h?fffh memb.@l ports 0?6 and bsc fc0h?fffh @ h+da.b all bit- manipulable peripheral hardware all bits of the memory bank specified by emb and smb that are bit- manipulable instructions which have skip conditions the following instructions have a skip function when an overflow or borrow occurs: xchi incs xchd decs ldi ads ldd sbs if there is an overflow or borrow from the result of an increment or decrement, a skip signal is generated and a skip is executed. however, the carry flag value is unaffected. the instructions btst, btsf, and cpse also generate a skip signal and execute a skip when they meet a skip condition, and the carry flag value is also unaffected. instructions which affect the carry flag the only instructions which do not generate a skip signal, but which do affect the carry flag are as follows: adc ldb c,(operand) sbc band c,(operand) scf bor c,(operand) rcf bxor c,(operand) ccf iret rrc
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 5 adc and sbc instruction skip conditions the instructions 'adc a,@hl' and 'sbc a,@hl' can generate a skip signal, and set or clear the carry flag, when they are executed in combination with the instruction 'ads a,#im'. if an 'ads a,#im' instruction immediately follows an 'adc a,@hl' or 'sbc a,@hl' instruction in a program sequence, the ads instruction does not skip the instruction following ads, even if it has a skip function. if, how - ever, an 'adc a,@hl' or 'sbc a,@hl' instruction is immediately followed by an 'ads a,#im' instruction, the adc (or sbc) skips on overflow (or if there is no borrow) to the instruction immediately following the ads, and program execution continues. table 5?3 contains additional information and examples of the 'adc a,@hl' and 'sbc a,@hl' skip feature. table 5?3. skip conditions for adc and sbc instructions sample instruction sequences if the result of instruction 1 is: then, the execution sequence is: reason adc a,@hl ads a,#im xxx xxx 1 2 3 4 overflow no overflow 1, 3, 4 1, 2, 3, 4 ads cannot skip instruction 3, even if it has a skip function. sbc a,@hl ads a,#im xxx xxx 1 2 3 4 borrow no borrow 1, 2, 3, 4 1, 3, 4 ads cannot skip instruc tion 3, even if it has a skip function.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 6 symbols and conventions table 5?4. data type symbols symbol data type d immediate data a address data b bit data r register data f flag data i indirect addressing data t memc x 0.5 immediate data table 5?5. register identifiers full register name id 4-bit accumulator a 4-bit working registers e, l, h, x, w, z, y 8-bit extended accumulator ea 8-bit memory pointer hl 8-bit working registers wx, yz, wl select register bank 'n' srb n select memory bank 'n' smb n carry flag c program status word psw port 'n' pn 'm'- th bit of port 'n' pn.m interrupt priority register ipr enable memory bank flag emb enable register bank flag erb table 5?6. instruction operand notation symbol definition da direct address @ indirect address prefix src source operand dst destination operand (r) contents of register r .b bit location im 4-bit immediate data (number) imm 8-bit immediate data (number) # immediate data prefix adr 000h?1fffh immediate address adrn 'n' bit address r a, e, l, h, x, w, z, y ra e, l, h, x, w, z, y rr ea, hl, wx, yz rra hl, wx, wl rrb hl, wx, yz rrc wx, wl mema fb0h?fbfh, ff0h?fffh memb fc0h?fffh memc code direct addressing: 0020h?007fh sb select bank register (8 bits) xor logical exclusive-or or logical or and logical and [(rr)] contents addressed by rr
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 7 opcode definitions table 5?7. opcode definitions (direct) register r2 r1 r0 a 0 0 0 e 0 0 1 l 0 1 0 h 0 1 1 x 1 0 0 w 1 0 1 z 1 1 0 y 1 1 1 ea 0 0 0 hl 0 1 0 wx 1 0 0 yz 1 1 0 r = immediate data for register table 5?8. opcode definitions (indirect) register i2 i1 i0 @hl 1 0 1 @wx 1 1 0 @wl 1 1 1 calculating additional machine cycles for skips a machine cycle is defined as one cycle of the selected cpu clock. three different clock rates can be selected using the pcon register. in this document, the letter 's' is used in tables when describing the number of additional machine cycles re - quired for an instruction to execute, given that the instruction has a skip function ('s' = skip). the addition number of machine cycles that will be required to perform the skip usually depends on the size of the instruction being skipped ? whether it is a 1-byte, 2-byte, or 3-byte instruction. a skip is also done for smb and srb instructions. the possible values in additional machine cycles for 's' for the three cases in which skip conditions occur are as follows: case 1: no skip s = 0 cycles case 2: skip is 1-byte or 2-byte instruction s = 1 cycle case 3: skip is 3-byte instruction s = 2 cycles please note that ref instructions are skipped in one machine cycle. i = immediate data for indirect addressing
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 8 high-level summary this section contains a high-level summary of the ks57 instruction set in table format. the tables are designed to familiarize you with the range of instructions that are available in each instruction category. you can also use these tables as a quick-reference source when writing application programs. the following general information is provided for each instruction: ? instruction name ? operand(s) ? brief operation description ? number of bytes of the instruction and operand(s) ? number of machine cycles required to execute the instruction the tables in this section are arranged according to the following instruction categories: ? cpu control instructions ? program control instructions ? data transfer instructions ? logic instructions ? arithmetic instructions ? bit manipulation instructions
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 9 table 5?9. cpu control instructions ? high-level summary name operand operation description bytes cycles scf set carry flag to logic one 1 1 rcf reset carry flag to logic zero 1 1 ccf complement carry flag 1 1 ei enable all interrupts 2 2 di disable all interrupts 2 2 idle engage cpu idle mode 2 2 stop engage cpu stop mode 2 2 nop no operation 1 1 smb n select memory bank 2 2 srb n select register bank 2 2 ref memc reference code 1 3 ventn emb (0,1) erb (0,1) adr load enable memory bank flag (emb) and the enable register bank flag (erb) and program counter to vector address, then branch to the corresponding location 2 2 table 5?10. program control instructions ? high-level summary name operand operation description bytes cycles cpse r,#im compare and skip if register equals # im 2 2 + s @ hl,#im compare and skip if indirect data memory equals # im 2 2 + s a,r compare and skip if a equals r 2 2 + s a,@hl compare and skip if a equals indirect data memory 1 1 + s ea,@hl compare and skip if ea equals indirect data memory 2 2 + s ea,rr compare and skip if ea equals rr 2 2 + s jp adr14 jump to direct address (14 bits) 3 3 jps adr12 jump direct in page (12 bits) 2 2 jr # im jump to immediate address 1 2 @wx branch relative to wx register 2 3 @ea branch relative to ea 2 3 call adr14 call direct in page (14 bits) 3 4 calls adr11 call direct in page (11 bits) 2 3 ret ? return from subroutine 1 3 iret ? return from interrupt 1 3 sret ? return from subroutine and skip 1 3 + s
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 10 table 5?11. data transfer instructions ? high-level summary name operand operation description bytes cycles xch a,da exchange a and direct data memory contents 2 2 a,ra exchange a and register ( ra) contents 1 1 a,@rra exchange a and indirect data memory 1 1 ea,da exchange ea and direct data memory contents 2 2 ea,rrb exchange ea and register pair ( rrb) contents 2 2 ea,@hl exchange ea and indirect data memory contents 2 2 xchi a,@hl exchange a and indirect data memory contents; increment contents of register l and skip on carry 1 2 + s xchd a,@hl exchange a and indirect data memory contents; decrement contents of register l and skip on carry 1 2 + s ld a,#im load 4-bit immediate data to a 1 1 a,@rra load indirect data memory contents to a 1 1 a,da load direct data memory contents to a 2 2 a,ra load register contents to a 2 2 ra,#im load 4-bit immediate data to register 2 2 rr,#imm load 8-bit immediate data to register 2 2 da,a load contents of a to direct data memory 2 2 ra,a load contents of a to register 2 2 ea,@hl load indirect data memory contents to ea 2 2 ea,da load direct data memory contents to ea 2 2 ea,rrb load register contents to ea 2 2 @hl,a load contents of a to indirect data memory 1 1 da,ea load contents of ea to data memory 2 2 rrb,ea load contents of ea to register 2 2 @hl,ea load contents of ea to indirect data memory 2 2 ldi a,@hl load indirect data memory to a; increment register l contents and skip on carry 1 2 + s ldd a,@hl load indirect data memory contents to a; decrement register l contents and skip on carry 1 2 + s ldc ea,@wx load code byte from wx to ea 1 3 ea,@ea load code byte from ea to ea 1 3 rrc a rotate right through carry bit 1 1 push rr push register pair onto stack 1 1 sb push smb and srb values onto stack 2 2 pop rr pop to register pair from stack 1 1 sb pop smb and srb values from stack 2 2
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 11 table 5?12. logic instructions ? high-level summary name operand operation description bytes cycles and a,#im logical-and a immediate data to a 2 2 a,@hl logical-and a indirect data memory to a 1 1 ea,rr logical-and register pair (rr) to ea 2 2 rrb,ea logical-and ea to register pair ( rrb) 2 2 or a, # im logical-or immediate data to a 2 2 a, @hl logical-or indirect data memory contents to a 1 1 ea,rr logical-or double register to ea 2 2 rrb,ea logical-or ea to double register 2 2 xor a,#im exclusive-or immediate data to a 2 2 a,@hl exclusive-or indirect data memory to a 1 1 ea,rr exclusive-or register pair (rr) to ea 2 2 rrb,ea exclusive-or register pair ( rrb) to ea 2 2 com a complement accumulator (a) 2 2 table 5?13. arithmetic instructions ? high-level summary name operand operation description bytes cycles adc a,@hl add indirect data memory to a with carry 1 1 ea,rr add register pair (rr) to ea with carry 2 2 rrb,ea add ea to register pair ( rrb) with carry 2 2 ads a, # im add 4-bit immediate data to a and skip on carry 1 1 + s ea,#imm add 8-bit immediate data to ea and skip on carry 2 2 + s a,@hl add indirect data memory to a and skip on carry 1 1 + s ea,rr add register pair (rr) contents to ea and skip on carry 2 2 + s rrb,ea add ea to register pair ( rrb) and skip on carry 2 2 + s sbc a,@hl subtract indirect data memory from a with carry 1 1 ea,rr subtract register pair (rr) from ea with carry 2 2 rrb,ea subtract ea from register pair ( rrb) with carry 2 2 sbs a,@hl subtract indirect data memory from a; skip on borrow 1 1 + s ea,rr subtract register pair (rr) from ea; skip on borrow 2 2 + s rrb,ea subtract ea from register pair ( rrb); skip on borrow 2 2 + s decs r decrement register (r); skip on borrow 1 1 + s rr decrement register pair (rr); skip on borrow 2 2 + s incs r increment register (r); skip on carry 1 1 + s da increment direct data memory; skip on carry 2 2 + s @hl increment indirect data memory; skip on carry 2 2 + s rrb increment register pair ( rrb); skip on carry 1 1 + s
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 12 table 5?14. bit manipulation instructions ? high-level summary name operand operation description bytes cycles btst c test specified bit and skip if carry flag is set 1 1 + s da.b test specified bit and skip if memory bit is set mema.b memb.@l @ h+da.b btsf da.b test specified memory bit and skip if bit equals "0" mema.b 2 2 + s memb.@l @ h+da.b btstz mema.b test specified bit; skip and clear if memory bit is set memb.@l @ h+da.b bits da.b set specified memory bit mema.b memb.@l @ h+da.b bitr da.b clear specified memory bit to logic zero mema.b memb.@l @ h+da.b band c,mema.b logical-and carry flag with specified memory bit c,memb.@l c,@h+da.b 2 2 bor c,mema.b logical-or carry with specified memory bit c,memb.@l c,@h+da.b bxor c,mema.b exclusive-or carry with specified memory bit c,memb.@l c,@h+da.b ldb mema.b,c load carry bit to a specified memory bit memb.@l,c load carry bit to a specified indirect memory bit @ h+da.b,c c,mema.b load specified memory bit to carry bit c,memb.@l load specified indirect memory bit to carry bit c,@h+da.b
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 13 binary code summary this section contains binary code values and operation notation for each instruction in the sam47 instruction set in an easy-to-read, tabular format. it is intended to be used as a quick-reference source for programmers who are experienced with the sam47 instruction set. the same binary values and notation are also included in the detailed descriptions of individual instructions later in section 5. if you are reading this user's manual for the first time, please just scan this very detailed information briefly. most of the general information you will need to write application programs can be found in the high-level summary tables in the previous section. the following information is provided for each instruction: ? instruction name ? operand(s) ? binary values ? operation notation the tables in this section are arranged according to the following instruction categories: ? cpu control instructions ? program control instructions ? data transfer instructions ? logic instructions ? arithmetic instructions ? bit manipulation instructions
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 14 table 5?15. cpu control instructions ? binary code summary name operand binary code operation notation scf 1 1 1 0 0 1 1 1 c ? 1 rcf 1 1 1 0 0 1 1 0 c ? 0 ccf 1 1 0 1 0 1 1 0 c ? c ei 1 1 1 1 1 1 1 1 ime ? 1 1 0 1 1 0 0 1 0 di 1 1 1 1 1 1 1 0 ime ? 0 1 0 1 1 0 0 1 0 idle 1 1 1 1 1 1 1 1 pcon.2 ? 1 1 0 1 0 0 0 1 1 stop 1 1 1 1 1 1 1 1 pcon.3 ? 1 1 0 1 1 0 0 1 1 nop 1 0 1 0 0 0 0 0 no operation smb n 1 1 0 1 1 1 0 1 smb ? n (n = 0, 1, 15) 0 1 0 0 d3 d2 d1 d0 srb n 1 1 0 1 1 1 0 1 srb ? n (n = 0, 1, 2, 3) 0 1 0 1 0 0 d1 d0 ref memc t7 t6 t5 t4 t3 t2 t1 t0 pc13?0 = memc7?4, memc3?0 <1 ventn emb (0,1) erb (0,1) adr e m b e r b a13 a12 a11 a10 a9 a8 rom (2 x n) 7?6 ? emb, erb rom (2 x n) 5?4 ? 0, pc13, pc12 rom (2 x n) 3?0 ? pc12?8 rom (2 x n + 1) 7?0 ? pc7?0 (n = 0, 1, 2, 3, 4, 5, 6, 7) a7 a6 a5 a4 a3 a2 a1 a0
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 15 table 5?16. program control instructions ? binary code summary name operand binary code operation notation cpse r,#im 1 1 0 1 1 0 0 1 skip if r = im d3 d2 d1 d0 0 r2 r1 r0 @ hl,#im 1 1 0 1 1 1 0 1 skip if (hl) = im 0 1 1 1 d3 d2 d1 d0 a,r 1 1 0 1 1 1 0 1 skip if a = r 0 1 1 0 1 r2 r1 r0 a,@hl 0 0 1 1 1 0 0 0 skip if a = (hl) ea,@hl 1 1 0 1 1 1 0 0 skip if a = (hl), e = (hl+1) 0 0 0 0 1 0 0 1 ea,rr 1 1 0 1 1 1 0 0 skip if ea = rr 1 1 1 0 1 r2 r1 0 jp adr14 1 1 0 1 1 0 1 1 pc13?0 ? adr14 0 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 jps adr12 1 0 0 1 a11 a10 a9 a8 pc13?0 ? pc13?12 + adr11?0 a7 a6 a5 a4 a3 a2 a1 a0 jr # im * pc13?0 ? adr (pc?15 to pc+16) @wx 1 1 0 1 1 1 0 1 pc13?0 ? pc13?8 + (wx) 0 1 1 0 0 1 0 0 @ea 1 1 0 1 1 1 0 1 pc13?0 ? pc13?8 + (ea) 0 1 1 0 0 0 0 0 call adr14 1 1 0 1 1 0 1 1 [(sp?1) (sp?2)] ? emb, erb 0 1 a13 a12 a11 a10 a9 a8 [(sp?3) (sp?4)] ? pc7?0 a7 a6 a5 a4 a3 a2 a1 a0 [(sp?5) (sp?6)] ? pc13?8 calls adr11 1 1 1 0 1 a10 a9 a8 [(sp?1) (sp?2)] ? emb, erb a7 a6 a5 a4 a3 a2 a1 a0 [(sp?3) (sp?4)] ? pc7?0 [(sp?5) (sp?6)] ? pc10?8 first byte condition * jr # im 0 0 0 1 a3 a2 a1 a0 pc ? pc+2 to pc+16 0 0 0 0 a3 a2 a1 a0 pc ? pc?1 to pc?15
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 16 table 5?16. program control instructions ? binary code summary (continued) name operand binary code operation notation ret ? 1 1 0 0 0 1 0 1 pc13?8 ? (sp + 1) (sp) pc7?0 ? (sp + 2) (sp + 3) emb,erb ? (sp + 5) (sp + 4) sp ? sp + 6 iret ? 1 1 0 1 0 1 0 1 pc13?8 ? (sp + 1) (sp) pc7?0 ? (sp + 2) (sp + 3) psw ? (sp + 4) (sp + 5) sp ? sp + 6 sret ? 1 1 1 0 0 1 0 1 pc13?8 ? (sp + 1) (sp) pc7?0 ? (sp + 3) (sp + 2) emb,erb ? (sp + 5) (sp + 4) sp ? sp + 6 table 5?17. data transfer instructions ? binary code summary name operand binary code operation notation xch a,da 0 1 1 1 1 0 0 1 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 0 1 1 0 1 r2 r1 r0 a ? ra a,@rra 0 1 1 1 1 i2 i1 i0 a ? ( rra) ea,da 1 1 0 0 1 1 1 1 a ? da,e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 0 0 r2 r1 0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 0 0 0 1 xchi a,@hl 0 1 1 1 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h xchd a,@hl 0 1 1 1 1 0 1 1 a ? (hl), then l ? l-1; skip if l = 0fh ld a,#im 1 0 1 1 d3 d2 d1 d0 a ? im a,@rra 1 0 0 0 1 i2 i1 i0 a ? ( rra) a,da 1 0 0 0 1 1 0 0 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 1 1 0 1 1 1 0 1 a ? ra 0 0 0 0 1 r2 r1 r0
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 17 table 5?17. data transfer instructions ? binary code summary (continued) name operand binary code operation notation ld ra,#im 1 1 0 1 1 0 0 1 ra ? im d3 d2 d1 d0 1 r2 r1 r0 rr,#imm 1 0 0 0 0 r2 r1 1 rr ? imm d7 d6 d5 d4 d3 d2 d1 d0 da,a 1 0 0 0 1 0 0 1 da ? a a7 a6 a5 a4 a3 a2 a1 a0 ra,a 1 1 0 1 1 1 0 1 ra ? a 0 0 0 0 0 r2 r1 r0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 1 0 0 0 ea,da 1 1 0 0 1 1 1 0 a ? da, e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 1 1 r2 r1 0 @hl,a 1 1 0 0 0 1 0 0 (hl) ? a da,ea 1 1 0 0 1 1 0 1 da ? a, da + 1 ? e a7 a6 a5 a4 a3 a2 a1 a0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? ea 1 1 1 1 0 r2 r1 0 @hl,ea 1 1 0 1 1 1 0 0 (hl) ? a, (hl + 1) ? e 0 0 0 0 0 0 0 0 ldi a,@hl 1 0 0 0 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h ldd a,@hl 1 0 0 0 1 0 1 1 a ? (hl), then l ? l?1; skip if l = 0fh ldc ea,@wx 1 1 0 0 1 1 0 0 ea ? [pc13?8 + (wx)] ea,@ea 1 1 0 0 1 0 0 0 ea ? [pc13?8 + (ea)] rrc a 1 0 0 0 1 0 0 0 c ? a.0, a3 ? c a.n?1 ? a.n (n = 1, 2, 3) push rr 0 0 1 0 1 r2 r1 1 ((sp?1)) ((sp?2)) ? (rr), (sp) ? (sp)?2 sb 1 1 0 1 1 1 0 1 ((sp?1)) ? (smb), ((sp?2)) ? (srb), (sp) ? (sp)?2 0 1 1 0 0 1 1 1
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 18 table 5?17. data transfer instructions ? binary code summary (concluded) name operand binary code operation notation pop rr 0 0 1 0 1 r2 r1 0 rr l ? (sp), rr h ? (sp + 1) sp ? sp + 2 sb 1 1 0 1 1 1 0 1 (srb) ? (sp), smb ? (sp + 1), sp ? sp + 2 0 1 1 0 0 1 1 0 table 5?18. logic instructions ? binary code summary name operand binary code operation notation and a,#im 1 1 0 1 1 1 0 1 a ? a and im 0 0 0 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 0 1 a ? a and (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea and rr 0 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb and ea 0 0 0 1 0 r2 r1 0 or a, # im 1 1 0 1 1 1 0 1 a ? a or im 0 0 1 0 d3 d2 d1 d0 a, @hl 0 0 1 1 1 0 1 0 a ? a or (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea or rr 0 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb or ea 0 0 1 0 0 r2 r1 0 xor a,#im 1 1 0 1 1 1 0 1 a ? a xor im 0 0 1 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 1 1 a ? a xor (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea xor (rr) 0 0 1 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb xor ea 0 0 1 1 0 r2 r1 0 com a 1 1 0 1 1 1 0 1 a ? a 0 0 1 1 1 1 1 1
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 19 table 5?19. arithmetic instructions ? binary code summary name operand binary code operation notation adc a,@hl 0 0 1 1 1 1 1 0 c, a ? a + (hl) + c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea + rr + c 1 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c, rrb ? rrb + ea + c 1 0 1 0 0 r2 r1 0 ads a, # im 1 0 1 0 d3 d2 d1 d0 a ? a + im; skip on carry ea,#imm 1 1 0 0 1 0 0 1 ea ? ea + imm; skip on carry d7 d6 d5 d4 d3 d2 d1 d0 a,@hl 0 0 1 1 1 1 1 1 a ? a + (hl); skip on carry ea,rr 1 1 0 1 1 1 0 0 ea ? ea + rr; skip on carry 1 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb + ea; skip on carry 1 0 0 1 0 r2 r1 0 sbc a,@hl 0 0 1 1 1 1 0 0 c,a ? a ? (hl) ? c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea ?rr ? c 1 1 0 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c,rrb ? rrb ? ea ? c 1 1 0 0 0 r2 r1 0 sbs a,@hl 0 0 1 1 1 1 0 1 a ? a ? (hl); skip on borrow ea,rr 1 1 0 1 1 1 0 0 ea ? ea ? rr; skip on borrow 1 0 1 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb ? ea; skip on borrow 1 0 1 1 0 r2 r1 0 decs r 0 1 0 0 1 r2 r1 r0 r ? r?1; skip on borrow rr 1 1 0 1 1 1 0 0 rr ? rr?1; skip on borrow 1 1 0 1 1 r2 r1 0 incs r 0 1 0 1 1 r2 r1 r0 r ? r + 1; skip on carry da 1 1 0 0 1 0 1 0 da ? da + 1; skip on carry a7 a6 a5 a4 a3 a2 a1 a0 @hl 1 1 0 1 1 1 0 1 (hl) ? (hl) + 1; skip on carry 0 1 1 0 0 0 1 0 rrb 1 0 0 0 0 r2 r1 0 rrb ? rrb + 1; skip on carry
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 20 table 5?20. bit manipulation instructions ? binary code summary name operand binary code operation notation btst c 1 1 0 1 0 1 1 1 skip if c = 1 da.b 1 1 b1 b0 0 0 1 1 skip if da.b = 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 1 skip if mema.b = 1 memb.@l 1 1 1 1 1 0 0 1 skip if [memb.7?2 + l.3?2]. [l.1?0] = 1 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 0 0 1 skip if [h + da.3?0].b = 1 0 0 b1 b0 a3 a2 a1 a0 btsf da.b 1 1 b1 b0 0 0 1 0 skip if da.b = 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 0 skip if mema.b = 0 memb.@l 1 1 1 1 1 0 0 0 skip if [memb.7?2 + l.3?2]. [l.1?0] = 0 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 0 0 0 skip if [h + da.3?0].b = 0 0 0 b1 b0 a3 a2 a1 a0 btstz mema.b * 1 1 1 1 1 1 0 1 skip if mema.b = 1 and clear memb.@l 1 1 1 1 1 1 0 1 skip if [memb.7?2 + l.3?2]. [l.1?0] = 1 and clear 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 0 1 skip if [h + da.3?0].b =1 and clear 0 0 b1 b0 a3 a2 a1 a0 bits da.b 1 1 b1 b0 0 0 0 1 da.b ? 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 1 mema.b ? 1 memb.@l 1 1 1 1 1 1 1 1 [memb.7?2 + l.3?2].b [l.1?0] ? 1 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 1 1 [h + da.3?0].b ? 1 0 0 b1 b0 a3 a2 a1 a0
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 21 table 5?20. bit manipulation instructions ? binary code summary (continued) name operand binary code operation notation bitr da.b 1 1 b1 b0 0 0 0 0 da.b ? 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 0 mema.b ? 0 memb.@l 1 1 1 1 1 1 1 0 [memb.7?2 + l3?2].[l.1?0] ? 0 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 1 0 [h + da.3?0].b ? 0 0 0 b1 b0 a3 a2 a1 a0 band c,mema.b * 1 1 1 1 0 1 0 1 c ? c and mema.b c,memb.@l 1 1 1 1 0 1 0 1 c ? c and [memb.7?2 + l.3?2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 1 c ? c and [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 bor c,mema.b * 1 1 1 1 0 1 1 0 c ? c or mema.b c,memb.@l 1 1 1 1 0 1 1 0 c ? c or [memb.7?2 + l.3?2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 0 c ? c or [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 bxor c,mema.b * 1 1 1 1 0 1 1 1 c ? c xor mema.b c,memb.@l 1 1 1 1 0 1 1 1 c ? c xor [memb.7?2 + l.3?2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 1 c ? c xor [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 22 table 5?20. bit manipulation instructions ? binary code summary (concluded) name operand binary code operation notation ldb mema.b,c * 1 1 1 1 1 1 0 0 mema.b ? c memb.@l,c 1 1 1 1 1 1 0 0 memb.7?2 + [l.3?2]. [l.1?0] ? c 0 1 0 0 a5 a4 a3 a2 @ h+da.b,c 1 1 1 1 1 1 0 0 h + [da.3?0].b ? (c) 0 b2 b1 b0 a3 a2 a1 a0 c,mema.b * 1 1 1 1 0 1 0 0 c ? mema.b c,memb.@l 1 1 1 1 0 1 0 0 c ? memb.7?2 + [l.3?2] . [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 0 c ? [h + da.3?0].b 0 b2 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 23 instruction descriptions the following section contains detailed information and programming examples for each instruction of the sam47 instruction set. information is arranged in a consistent format to improve readability and for use as a quick-reference resource for application programmers. if you are reading this user's manual for the first time, please just scan this very detailed information in order to acquaint yourself with the basic features of the instruction set. the information elements of the instruction description format are as follows: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? operation overview (from the "high-level summary" table) ? textual description of the instruction's effect ? binary code overview (from the "binary code summary" table) ? programming example(s) to show how the instruction is used
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 24 adc ? ? add with carry adc dst,src operation: operand operation summary bytes cycles a,@hl add indirect data memory to a with carry 1 1 ea,rr add register pair (rr) to ea with carry 2 2 rrb,ea add ea to register pair ( rrb) with carry 2 2 description: the source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. if there is an overflow from the most significant bit of the result, the carry flag is set; otherwise, the carry flag is cleared. if 'adc a,@hl' is followed by an 'ads a,#im' instruction in a program, adc skips the ads instruction if an overflow occurs. if there is no overflow, the ads instruction is executed normally. (this condition is valid only for 'adc a,@hl' instructions. if an overflow occurs following an 'ads a,#im' instruction, the next instruction will not be skipped.) operand binary code operation notation a,@hl 0 0 1 1 1 1 1 0 c, a ? a + (hl) + c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea + rr + c 1 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c, rrb ? rrb + ea + c 1 0 1 0 0 r2 r1 0 examples: 1. the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag is set to "1": scf ; c ? "1" adc ea,hl ; ea ? 0c3h + 0aah + 1h = 6eh, c ? "1" jps xxx ; jump to xxx; no skip after adc 2. if the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag is cleared to "0": rcf ; c ? "0" adc ea,hl ; ea ? 0c3h + 0aah + 0h = 6eh, c ? "1" jps xxx ; jump to xxx; no skip after adc
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 25 adc ? ? add with carry adc (continued) examples: 3. if adc a,@hl is followed by an ads a,#im, the adc skips on carry to the instruction immediately after the ads. an ads instruct ion immediately after the adc does not skip even if an overflow occurs. this function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the hl register is 9h): rcf ; c ? "0" ld a,#8h ; a ? 8h ads a,#6h ; a ? 8h + 6h = 0eh adc a,@hl ; a ? 7h, c ? "1" ads a,#0ah ; skip this instruction because c = "1" after adc result jps xxx b. 3 + 4 decimal addition (the contents of the address specified by the hl register is 4h): rcf ; c ? "0" ld a,#3h ; a ? 3h ads a,#6h ; a ? 3h + 6h = 9h adc a,@hl ; a ? 9h + 4h + c(0) = 0dh ads a,#0ah ; no skip. a ? 0dh + 0ah = 7h ; (the skip function for 'ads a,#im' is inhibited after an ; 'adc a,@hl' instruction even if an overflow occurs.) jps xxx
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 26 ads ? ? add and skip on overflow ads dst,src operation: operand operation summary bytes cycles a, # im add 4-bit immediate data to a and skip on overflow 1 1 + s ea,#imm add 8-bit immediate data to ea and skip on overflow 2 2 + s a,@hl add indirect data memory to a and skip on overflow 1 1 + s ea,rr add register pair (rr) contents to ea and skip on overflow 2 2 + s rrb,ea add ea to register pair ( rrb) and skip on overflow 2 2 + s description: the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. if there is an overflow from the most significant bit of the result, the skip signal is generated and a skip is executed, but the carry flag value is unaffected. if 'ads a,#im' follows an 'adc a,@hl' instruction in a program, adc skips the ads instruction if an overflow occurs. if there is no overflow, the ads instruction is executed normally. this skip condition is valid only for 'adc a,@hl' instructions, however. if an overflow occurs following an ads instruction, the next instruction is not skipped. operand binary code operation notation a, # im 1 0 1 0 d3 d2 d1 d0 a ? a + im; skip on overflow ea,#imm 1 1 0 0 1 0 0 1 ea ? ea + imm; skip on overflow d7 d6 d5 d4 d3 d2 d1 d0 a,@hl 0 0 1 1 1 1 1 1 a ? a + (hl); skip on overflow ea,rr 1 1 0 1 1 1 0 0 ea ? ea + rr; skip on overflow 1 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb + ea; skip on overflow 1 0 0 1 0 r2 r1 0 examples: 1. the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag = "0": ads ea,hl ; ea ? 0c3h + 0aah = 6dh, c ? "0" ; ads skips on overflow, but carry flag value is not affected. jps xxx ; this instruction is skipped because ads overflowed. jps yyy ; jump to yyy.
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 27 ads ? ? add and skip on overflow ads (continued) examples: 2. if the extended accumulator contains the value 0c3h, register pair hl the value 12h, and the carry flag = "0": ads ea,hl ; ea ? 0c3h + 12h = 0d5h, c ? "0" jps xxx ; jump to xxx; no skip after ads. 3. if 'adc a,@hl' is followed by an 'ads a,#im', the adc skips on overflow to the instruction immediately after the ads. an 'ads a,#im' instruction immediately after the 'adc a,@hl' does not skip even if overflow occurs. this function is useful for decimal adjustment operations. a. 8 + 9 decimal addition (the contents of the address specified by the hl register is 9h): rcf ; c ? "0" ld a,#8h ; a ? 8h ads a,#6h ; a ? 8h + 6h = 0eh adc a,@hl ; a ? 7h, c ? "1" ads a,#0ah ; skip this instruction because c = "1" after adc result. jps xxx b. 3 + 4 decimal addition (the contents of the address specified by the hl register is 4h): rcf ; c ? "0" ld a,#3h ; a ? 3h ads a,#6h ; a ? 3h + 6h = 9h adc a,@hl ; a ? 9h + 4h + c(0) = 0dh ads a,#0ah ; no skip. a ? 0dh + 0ah = 7h ; (the skip function for 'ads a,#im' is inhibited after an ; 'adc a,@hl' instruction even if an overflow occurs.) jps xxx
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 28 and ? ? logical and and dst,src operation: operand operation summary bytes cycles a,#im logical-and a immediate data to a 2 2 a,@hl logical-and a indirect data memory to a 1 1 ea,rr logical-and register pair (rr) to ea 2 2 rrb,ea logical-and ea to register pair ( rrb) 2 2 description: the source operand is logically anded with the destination operand. the result is stored in the destination. the logical and operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both "1"; otherwise a "0" bit is stored. the contents of the source are unaffected. operand binary code operation notation a,#im 1 1 0 1 1 1 0 1 a ? a and im 0 0 0 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 0 1 a ? a and (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea and rr 0 0 0 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb and ea 0 0 0 1 0 r2 r1 0 example: if the extended accumulator contains the value 0c3h (11000011b) and register pair hl the value 55h (01010101b), the instruction and ea,hl leaves the value 41h (01000001b) in the extended accumulator ea .
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 29 band ? ? bit logical and band c,src.b operation: operand operation summary bytes cycles c,mema.b logical-and carry flag with memory bit 2 2 c,memb.@l 2 2 c,@h+da.b 2 2 description: the specified bit of the source is logically anded with the carry flag bit value. if the boolean value of the source bit is a logic zero, the carry flag is cleared to "0"; otherwise, the current carry flag setting is left unaltered. the bit value of the source operand is not affected. operand binary code operation notation c,mema.b * 1 1 1 1 0 1 0 1 c ? c and mema.b c,memb.@l 1 1 1 1 0 1 0 1 c ? c and [memb.7?2 + l.3? 2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 1 c ? c and [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. the following instructions set the carry flag if p1.0 (port 1.0) is equal to "1" (and assuming the carry flag is already set to "1"): smb 15 ; c ? "1" band c,p1.0 ; if p1.0 = "1", c ? "1" ; if p1.0 = "0", c ? "0"
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 30 band ? ? bit logical and band (continued) examples: 2. assume the p1 addre ss is ff1h and the value for register l is 9h (1001b). the address (memb.7 ?2) is 111100b; (l.3?2) is 10b. the resulting address is 11110010b or ff2h, specifying p2. the bit value for the band instruction, (l.1?0) is 01b which specifies bit 1. therefore, p1.@l = p2.1: ld l,#9h band c,p1.@l ; p1.@l is specified as p2.1 ; c and p2.1 3. register h contains the value 2h and flag = 20h.3. the address of h is 0010b and flag(3 ?0) is 0000b. the resulting address is 00100000b or 20h. the bit value for the band instruction is 3. therefore, @h+flag = 20h.3: flag equ 20h.3 ld h,#2h band c,@h+flag ; c and flag (20h.3)
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 31 bitr ? ? bit reset bitr dst.b operation: operand operation summary bytes cycles da.b clear specified memory bit to logic zero 2 2 mema.b 2 2 memb.@l 2 2 @ h+da.b 2 2 description: a bitr instruction clears to logic zero (resets) the specified bit within the destination operand. no other bits in the destination are affected. operand binary code operation notation da.b 1 1 b1 b0 0 0 0 0 da.b ? 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 0 mema.b ? 0 memb.@l 1 1 1 1 1 1 1 0 [memb.7?2 + l3?2].[l.1?0] ? 0 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 1 0 [h + da.3?0].b ? 0 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. bit location 30h.2 in the ram has a current value of logic one. the following instruction clears the third bit in ram locatio n 30h (bit 2) to logic zero: bitr 30h.2 ; 30h.2 ? "0" 2. you can use bitr in the same way to manipulate a port address bit: bitr p2.0 ; p2.0 ? "0"
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 32 bitr ? ? bit reset bitr (continued) examples: 3. assuming that p2.2, p2.3, and p3.0 ?p3.3 are cleared to "0": ld l,#0ah bp2 bitr p0.@l ; first, p0.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2h.2 incs l jr bp2 4. if bank 0, location 0a0h.0 is cleared (and regardless of whether the emb value is logic zero), bitr has the following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah bitr @h+flag ; bank 0 (ah + 0h).0 = 0a0h.0 ? "0" note because the bitr instruction is used for output functions, the pin names used in the examples above may vary for different devices in the sam47 product family.
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 33 bits ? ? bit set bits dst.b operation: operand operation summary bytes cycles da.b set specified memory bit 2 2 mema.b 2 2 memb.@l 2 2 @ h+da.b 2 2 description: this instruction sets the specified bit within the destination without affecting any other bits in the destination. bits can manipulate any bit that is addressable using direct or indirect addressing modes. operand binary code operation notation da.b 1 1 b1 b0 0 0 0 1 da.b ? 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 1 1 1 mema.b ? 1 memb.@l 1 1 1 1 1 1 1 1 [memb.7?2 + l.3?2].b [l.1?0] ? 1 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 1 1 [h + da.3?0].b ? 1 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. assuming that bit location 30h.2 in the ram has a current value of "0", the following instruction sets the second bit of location 30h to "1". bits 30h.2 ; 30h.2 ? "1" 2. you can use bits in the same way to manipulate a port address bit: bits p2.0 ; p2.0 ? "1"
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 34 bits ? ? bit set bits (continued) examples: 3. given that p2.2, p2.3, and p3.0 ?p3.3 are set to "1": ld l,#0ah bp2 bits p0.@l ; first, p0.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2 h.2 incs l jr bp2 4. if bank 0, location 0a0h.0, is set to "1" and the emb = "0", bits has the following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah bits @h+flag ; bank 0 (ah + 0h).0 = 0a0h.0 ? "1" note because the bits instruction is used for output functions, pin names used in the examples above may vary for different devices in the sam47 product family.
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 35 bor ? ? bit logical or bor c,src.b operation: operand operation summary bytes cycles c,mema.b logical-or carry with specified memory bit 2 2 c,memb.@l 2 2 c,@h+da.b 2 2 description: the specified bit of the source is logically ored with the carry flag bit value. the value of the source is unaffected. operand binary code operation notation c,mema.b * 1 1 1 1 0 1 1 0 c ? c or mema.b c,memb.@l 1 1 1 1 0 1 1 0 c ? c or [memb.7?2 + l.3?2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 0 c ? c or [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. the carry flag is logically ored with the p1.0 value: rcf ; c ? "0" bor c,p1.0 ; if p1.0 = "1", then c ? "1"; if p1.0 = "0", then c ? "0" 2. the p1 address is ff1h and register l contains the value 9h (1001b). the address (memb.7?2) is 111100b and (l.3?2) = 10b. the resulting address is 11110010b or ff2h, specifying p2. the bit value for the bor instruction, (l.1?0) is 01b which specifies bit 1. therefore, p1.@l = p2.1: ld l,#9h bor c,p1.@l ; p1.@l is specified as p2.1; c or p2.1
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 36 bor ? ? bit logical or bor (continued) examples: 3. register h contains the value 2h and flag = 20h.3. the address of h is 0010b and flag(3 ?0) is 0000b. the resulting address is 00100000b or 20h. the bit value for the bor instruction is 3. therefore, @h+flag = 20h.3: flag equ 20h.3 ld h,#2h bor c,@h+flag ; c or flag (20h.3)
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 37 btsf ? ? bit test skip on false btsf dst.b operation: operand operation summary bytes cycles da.b test specified memory bit and skip if bit equals "0" 2 2 + s mema.b 2 2 + s memb.@l 2 2 + s @ h+da.b 2 2 + s description: the specified bit within the destination operand is tested. if it is a "0", the btsf instruction skips the instruction which immediately follows it; otherwise the instruction following the btsf is executed. the destination bit value is not affected. operand binary code operation notation da.b 1 1 b1 b0 0 0 1 0 skip if da.b = 0 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 0 skip if mema.b = 0 memb.@l 1 1 1 1 1 0 0 0 skip if [memb.7?2 + l.3-2]. [l.1?0] = 0 0 1 0 0 a5 a4 a3 a2 @h + da.b 1 1 1 1 1 0 0 0 skip if [h + da.3?0].b = 0 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. if ram bit location 30h.2 is set to logic zero, the following instruction sequence will cause the program to continue execution from the instruction identifed as label2: btsf 30h.2 ; if 30h.2 = "0", then skip ret ; if 30h.2 = "1", return jp label2 2. you can use btsf in the same way to manipulate a port pin address bit: btsf p2.0 ; if p2.0 = "0", then skip ret ; if p2.0 = "1", then return jp label3
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 38 btsf ? ? bit test and skip on false btsf (continued) examples: 3. p2.2, p2.3 and p3.0 ?p3.3 are tested: ld l,#0ah bp2 btsf p0.@l ; first, p0.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2h.2 ret incs l jr bp2 4. bank 0, location 0a0h.0, is tested and (regardless of the current emb value) btsf has the following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah btsf @h+flag ; if bank 0 (ah + 0h).0 = 0a0h.0 = "0", then skip ret ? ? ?
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 39 btst ? ? bit test and skip on true btst dst.b operation: operand operation summary bytes cycles c test carry bit and skip if set (= "1") 1 1 + s da.b test specified bit and skip if memory bit is set 2 2 + s mema.b 2 2 + s memb.@l 2 2 + s @ h+da.b 2 2 + s description: the specified bit within the destination operand is tested. if it is "1", the instruction that immediately follows the btst instruction is skipped; otherwise the instruction following the btst instruction is executed. the destination bit value is not affected. operand binary code operation notation c 1 1 0 1 0 1 1 1 skip if c = 1 da.b 1 1 b1 b0 0 0 1 1 skip if da.b = 1 a7 a6 a5 a4 a3 a2 a1 a0 mema.b * 1 1 1 1 1 0 0 1 skip if mema.b = 1 memb.@l 1 1 1 1 1 0 0 1 skip if [memb.7?2 + l.3?2]. [l.1?0] = 1 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 0 0 1 skip if [h + da.3?0].b = 1 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. if ram bit location 30h.2 is set to logic zero, the following instruction sequence will execute the ret instruction: btst 30h.2 ; if 30h.2 = "1", then skip ret ; if 30h.2 = "0", return jp label2
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 40 btst ? ? bit test and skip on true btst (continued) examples: 2. you can use btst in the sam e way to manipulate a port pin address bit: btst p2.0 ; if p2.0 = "1", then skip ret ; if p2.0 = "0", then return jp label3 3. assume that p2.2, p2.3 and p3.0 ?p3.3 are cleared to "0": ld l,#0ah bp2 btst p0.@l ; first, p0.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2h.2 ret incs l jr bp2 4. bank 0, location 0a0h.0, is tested and (regardless of the current emb value) btst has the following effect: flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah btst @h+flag ; if bank 0 (ah + 0h).0 = 0a0h.0 = "1", then skip ret ? ? ?
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 41 btstz ? ? bit test and skip on true; clear bit btstz dst.b operation: operand operation summary bytes cycles mema.b test specified bit; skip and clear if memory bit is set 2 2 + s memb.@l 2 2 + s @ h+da.b 2 2 + s description: the specified bit within the destination operand is tested. if it is a "1", the instruction immediately following the btstz instruction is skipped; otherwise the instruction following the btstz is executed. the destination bit value is cleared. operand binary code operation notation mema.b * 1 1 1 1 1 1 0 1 skip if mema.b = 1 and clear memb.@l 1 1 1 1 1 1 0 1 skip if [memb.7?2 + l.3?2]. [l.1?0] = 1 and clear 0 1 0 0 a5 a4 a3 a2 @ h+da.b 1 1 1 1 1 1 0 1 skip if [h + da.3?0].b =1 and clear 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. port pin p2.0 is toggled by checking the p2.0 value (level): btstz p2.0 ; if p2.0 = "1", then p2.0 ? "0" and skip bits p2.0 ; if p2.0 = "0", then p2.0 ? "1" jp label3 2. assume that port pins p2.2, p2.3 and p3.0 ?p3.3 are toggled: ld l,#0ah bp2 btstz p0.@l ; first, p0.@0ah = p2.2 ; (111100b) + 10b.10b = 0f2h.2 ret incs l jr bp2
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 42 btstz ? ? bit test and skip on true; clear bit btstz (continued) examples: 3. bank 0, location 0a0h.0, is tested and emb = "0": flag equ 0a0h.0 ? ? ? bitr emb ? ? ? ld h,#0ah btstz @h+flag ; if bank 0 (ah + 0h).0 = 0a0h.0 = "1", clear and skip bits @h+flag ; if 0a0h.0 = "0", then 0a0h.0 ? "1"
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 43 bxor ? ? bit exclusive or bxor c,src.b operation: operand operation summary bytes cycles c,mema.b exclusive-or carry with memory bit 2 2 c,memb.@l 2 2 c,@h+da.b 2 2 description: the specified bit of the source is logically xored with the carry bit value. the resultant bit is written to the carry flag. the source value is unaffected. operand binary code operation notation c,mema.b * 1 1 1 1 0 1 1 1 c ? c xor mema.b c,memb.@l 1 1 1 1 0 1 1 1 c ? c xor [memb.7?2 + l.3-2]. [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 1 1 c ? c xor [h + da.3?0].b 0 0 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh examples: 1. the carry flag is logically xored with the p1.0 value: rcf ; c ? "0" bxor c,p1.0 ; if p1.0 = "1", then c ? "1"; if p1.0 = "0", then c ? "0" 2. the p1 address is ff1h and register l contains the value 9h (1001b). the address (memb.7?2) is 111100b and (l.3?2) = 10b. the resulting address is 11110010b or ff2h, specifying p2. the bit value for the bxor instruction, (l.1?0) is 01b which specifies bit 1. therefore, p1.@l = p2.1: ld l,#9h bxor c,p1.@l ; p1.@l is specified as p2.1; c xor p2.1
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 44 bxor ? ? bit exclusive or bxor (continued) examples: 3. register h contains the value 2h and flag = 20h.3. the address of h is 0010b and flag(3 ?0) is 0000b. the resulting address is 00100000b or 20h. the bit value for the bor instruction is 3. therefore, @h+flag = 20h.3: flag equ 20h.3 ld h,#2h bxor c,@h+flag ; c xor flag (20h.3)
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 45 call ? ? call procedure call dst operation: operand operation summary bytes cycles adr14 call direct in page (14 bits) 3 4 description: call calls a subroutine located at the destination address. the instruction adds three to the program counter to generate the return address and then pushes the result onto the stack, decrementing the stack pointer by six. the emb and erb are also pushed to the stack. program execution continues with the instruction at this address. the subroutine may therefore begin anywhere in the full 16-kbyte program memory address space. operand binary code operation notation adr14 1 1 0 1 1 0 1 1 [(sp?1) (sp?2)] ? emb, erb 0 1 a13 a12 a11 a10 a9 a8 [(sp?3) (sp?4)] ? pc7?0 a7 a6 a5 a4 a3 a2 a1 a0 [(sp?5) (sp?6)] ? pc13?8 example: the stack pointer value is 00h and the label 'play' is assigned to program memory location 0e3fh. executing the instruction call play at location 0123h generates the following values: sp = 0fah 0ffh = 0h 0feh = emb, erb 0fdh = 2h 0fch = 6h 0fbh = 0h 0fah = 1h pc = 0e3fh data is written to stack locations 0ffh?0fah as follows: 0fah pc11 ? pc8 0fbh 0 0 pc13 ? pc12 0fch pc3 ? pc0 0fdh pc7 ? pc4 0feh 0 0 emb erb 0ffh 0 0 0 0
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 46 calls ? ? call procedure (short) calls dst operation: operand operation summary bytes cycles adr11 call direct in page (11 bits) 2 3 description: the calls instruction unconditionally calls a subroutine located at the indicated address. the instruction increments the pc twice to obtain the address of the following instruction. then, it pushes the result onto the stack, decrementing the stack pointer six times. the higher bits of the pc, with the exception of the lower 11 bits, are cleared. the subroutine call must therefore be located within the 2-kbyte block (0000h?07ffh) of program memory. operand binary code operation notation adr11 1 1 1 0 1 a10 a9 a8 [(sp?1) (sp?2)] ? emb, erb a7 a6 a5 a4 a3 a2 a1 a0 [(sp?3) (sp?4)] ? pc7?0 [(sp?5) (sp?6)] ? pc10?8 example: the stack pointer value is 00h and the label 'play' is assigned to program memory location 0345h. executing the instruction calls play at location 0123h will generate the following values: sp = 0fah 0ffh = 0h 0feh = emb, erb 0fdh = 2h 0fch = 5h 0fbh = 0h 0fah = 1h pc = 0345h data is written to stack locations 0ffh?0fah as follows: 0fah 0 pc10 ? pc8 0fbh 0 0 0 0 0fch pc3 ? pc0 0fdh pc7 ? pc4 0feh 0 0 emb erb 0ffh 0 0 0 0
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 47 ccf ? ? complement carry flag ccf operation: operand operation summary bytes cycles ? complement carry flag 1 1 description: the carry flag is complemented; if c = "1" it is changed to c = "0" and vice-versa. operand binary code operation notation ? 1 1 0 1 0 1 1 0 c ? c example: if the carry flag is logic zero, the instruction ccf changes the value to logic one.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 48 com ? ? complement accumulator com a operation: operand operation summary bytes cycles a complement accumulator (a) 2 2 description: the accumulator value is complemented; if the bit value of a is "1", it is changed to "0" and vice versa. operand binary code operation notation a 1 1 0 1 1 1 0 1 a ? a 0 0 1 1 1 1 1 1 example: if the accumulator contains the value 4h (0100b), the instruction com a leaves the value 0bh (1011b) in the accumulator.
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 49 cpse ? ? compare and skip if equal cpse dst,src operation: operand operation summary bytes cycles r,#im compare and skip if register equals # im 2 2 + s @ hl,#im compare and skip if indirect data memory equals # im 2 2 + s a,r compare and skip if a equals r 2 2 + s a,@hl compare and skip if a equals indirect data memory 1 1 + s ea,@hl compare and skip if ea equals indirect data memory 2 2 + s ea,rr compare and skip if ea equals rr 2 2 + s description: cpse compares the source operand (subtracts it from) the destination operand, and skips the next instruction if the values are equal. neither operand is affected by the comparison. operand binary code operation notation r,#im 1 1 0 1 1 0 0 1 skip if r = im d3 d2 d1 d0 0 r2 r1 r0 @ hl,#im 1 1 0 1 1 1 0 1 skip if (hl) = im 0 1 1 1 d3 d2 d1 d0 a,r 1 1 0 1 1 1 0 1 skip if a = r 0 1 1 0 1 r2 r1 r0 a,@hl 0 0 1 1 1 0 0 0 skip if a = (hl) ea,@hl 1 1 0 1 1 1 0 0 skip if a = (hl), e = (hl+1) 0 0 0 0 1 0 0 1 ea,rr 1 1 0 1 1 1 0 0 skip if ea = rr 1 1 1 0 1 r2 r1 0 example: the extended accumulator contains the value 34h and register pair hl contains 56h. the second instruction (ret) in the instruction sequence cpse ea,hl ret is not skipped. that is, the subroutine returns because the result of the comparison is 'not equal.'
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 50 decs ? ? decrement and skip on borrow decs dst operation: operand operation summary bytes cycles r decrement register (r); skip on borrow 1 1 + s rr decrement register pair (rr); skip on borrow 2 2 + s description: the destination is decremented by one. an original value of 00h will underflow to 0ffh. if a borrow occurs, a skip is executed. the carry flag value is unaffected. operand binary code operation notation r 0 1 0 0 1 r2 r1 r0 r ? r?1; skip on borrow rr 1 1 0 1 1 1 0 0 rr ? rr?1; skip on borrow 1 1 0 1 1 r2 r1 0 examples: 1. register pair hl contains the value 7fh (01111111b). the following instruction leaves the value 7eh in register pair hl: decs hl 2. register a contains the value 0h. the following instruction sequence leaves the value 0ffh in register a. because a "borrow" occurs, the 'call play1' instruction is skipped and the 'call play2' instruction is executed: decs a ; "borrow" occurs call play1 ; skipped call play2 ; executed
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 51 di ? ? disable interrupts di operation: operand operation summary bytes cycles ? disable all interrupts 2 2 description: bit 3 of the interrupt priority register ipr, ime, is cleared to logic zero, disabling all interrupts. interrupts can still set their respective interrupt status latches, but the cpu will not directly service them. operand binary code operation notation ? 1 1 1 1 1 1 1 0 ime ? 0 1 0 1 1 0 0 1 0 example: if the ime bit (bit 3 of the ipr) is logic one (e.g., all instructions are enabled), the instruction di sets the ime bit to logic zero, disabling all interrupts.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 52 ei ? ? enable interrupts ei operation: operand operation summary bytes cycles ? enable all interrupts 2 2 description: bit 3 of the interrupt priority register ipr (ime) is set to logic one. this allows all interrupts to be serviced when they occur, assuming they are enabled. if an interrupt's status latch was previously enabled by an interrupt, this interrupt can also be serviced. operand binary code operation notation ? 1 1 1 1 1 1 1 1 ime ? 1 1 0 1 1 0 0 1 0 example: if the ime bit (bit 3 of the ipr) is logic zero (e.g., all instructions are disabled), the instruction ei sets the ime bit to logic one, enabling all interrupts.
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 53 idle ? ? idle operation idle operation: operand operation summary bytes cycles ? engage cpu idle mode 2 2 description: idle causes the cpu clock to stop while the system clock continues oscillating by setting bit 2 of the power control register (pcon). after an idle instruction has been executed, peripheral hardware remains operative. in application programs, an idle instruction should be immediately followed by at least three nop instructions. this ensures an adequate time interval for the clock to stabilize before the next instruction is executed. operand binary code operation notation ? 1 1 1 1 1 1 1 1 pcon.2 ? 1 1 0 1 0 0 0 1 1 example: the instruction sequence idle nop nop nop sets bit 2 of the pcon register to logic one, stopping the cpu clock. the three nop instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 54 incs ? ? increment a nd skip o n carry incs dst operation: operand operation summary bytes cycles r increment register (r); skip on carry 1 1 + s da increment direct data memory; skip on carry 2 2 + s @hl increment indirect data memory; skip on carry 2 2 + s rrb increment register pair ( rrb); skip on carry 1 1 + s description: the instruction incs increments the value of the destination operand by one. an original value of 0fh will, for example, overflow to 00h. if a carry occurs, the next instruction is skipped. the carry flag value is unaffected. operand binary code operation notation r 0 1 0 1 1 r2 r1 r0 r ? r + 1; skip on carry da 1 1 0 0 1 0 1 0 da ? da + 1; skip on carry a7 a6 a5 a4 a3 a2 a1 a0 @hl 1 1 0 1 1 1 0 1 (hl) ? (hl) + 1; skip on carry 0 1 1 0 0 0 1 0 rrb 1 0 0 0 0 r2 r1 0 rrb ? rrb + 1; skip on carry example: register pair hl contains the value 7eh (01111110b). ram location 7eh contains 0fh. the instruction sequence incs @hl ; 7eh ? "0" incs hl ; skip incs @hl ; 7eh ? "1" leaves the register pair hl with the value 7eh and ram location 7eh with the value 1h. because a carry occurred, the second instruction is skipped. the carry flag value remains unchanged.
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 55 iret ? ? return from interrupt iret operation: operand operation summary bytes cycles ? return from interrupt 1 3 description: iret is used at the end of an interrupt service routine. it pops the pc values successively from the stack and restores them to the program counter. the stack pointer is incremented by six and the psw, enable memory bank (emb) bit, and enable register bank (erb) bit are also automatically restored to their pre-interrupt values. program execution continues from the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. if a lower-level or same-level interrupt was pending when the iret was executed, iret will be executed before the pending interrupt is processed. because the 'a14' bit of an interrupt return address is not stored in the stack, this bit location is always interpreted as a logic zero. the start address in the rom must for this reason be 3fffh. operand binary code operation notation ? 1 1 0 1 0 1 0 1 pc13?8 ? (sp + 1) (sp) pc7?0 ? (sp + 2) (sp + 3) psw ? (sp + 4) (sp + 5) sp ? sp + 6 example: the stack pointer contains the value 0fah. an interrupt is detected in the instruction at location 0122h. ram locations 0fdh, 0fch, and 0fah contain the values 2h, 3h, and 1h, respectively. the instruction iret leaves the stack pointer with the value 00h and the program returns to continue execution at location 123h. during a return from interrupt, data is popped from the stack to the program counter. the data in stack locations 0ffh?0fah is organized as follows: 0fah pc11 ? pc8 0fbh 0 0 pc13 ? pc12 0fch pc3 ? pc0 0fdh pc7 ? pc4 0feh is1 is0 emb erb 0ffh c sc2 sc1 sc0
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 56 jp ? ? jump jp dst operation: operand operation summary bytes cycles adr14 jump to direct address (14 bits) 3 3 description: jp causes an unconditional branch to the indicated address by replacing the contents of the program counter with the address specified in the destination operand. the destination can be anywhere in the 16-kbyte program memory address space. operand binary code operation notation adr14 1 1 0 1 1 0 1 1 pc13?0 ? adr14 0 0 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 example: the label 'syscon' is assigned to the instruction at program location 07ffh. the instruction jp syscon at location 0123h loads the program counter with the value 07ffh.
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 57 jps ? ? jump (short) jps dst operation: operand operation summary bytes cycles adr12 jump direct in page (12 bits) 2 2 description: jps causes an unconditional branch to the indicated address within the 4-kbyte program memory address space. bits 0?11 of the program counter are replaced with the directly specified address. the destination address for this jump is specified to the assembler by a label or by an actual address in program memory. operand binary code operation notation adr12 1 0 0 1 a11 a10 a9 a8 pc13?0 ? pc13?12 + adr11? 0 a7 a6 a5 a4 a3 a2 a1 a0 example: the label 'sub' is assigned to the instruction at program memory location 00ffh. the instruction jps sub at location 0eabh will load the program counter with the value 00ffh. normally, the jps instruction jumps to the address in the block in which the instruction is located. if the first byte of the instruction code is located at address xffeh or xfffh, the instruction will jump to the next block. if the instruction ' jps sub' were located instead at program memory address 0ffeh or 0fffh, the instruction ' jps sub' would load the pc with the value 10ffh, causing a program malfunction.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 58 jr ? ? jump relative (very short) jr dst operation: operand operation summary bytes cycles # im branch to relative immediate address 1 2 @wx branch relative to contents of wx register 2 3 @ea branch relative to contents of ea 2 3 description: jr causes the relative address to be added to the program counter and passes control to the instruction whose address is now in the pc. the range of the relative address is current pc ? 15 to current pc + 16. the destination address for this jump is specified to the assembler by a label, an actual address, or by immediate data using a plus sign (+) or a minus sign (?). for immediate addressing, the (+) range is from 2 to 16 and the (?) range is from ?1 to ?15. if a 0, 1, or any other number that is outside these ranges are used, the assembler interprets it as an error. for jr @wx and jr @ea branch relative instructions, the valid range for the relative address is 0h?0ffh. the destination address for these jumps can be specified to the assembler by a label that lies anywhere within the current 256-byte block. normally, the 'jr @wx' and 'jr @ea' instructions jump to the address in the page in which the instruction is located. however, if the first byte of the instruction code is located at address xxfeh or xxffh, the instruction will jump to the next page. operand binary code operation notation # im * pc13?0 ? adr (pc?15 to pc+16) @wx 1 1 0 1 1 1 0 1 pc13?0 ? pc13?8 + (wx) 0 1 1 0 0 1 0 0 @ea 1 1 0 1 1 1 0 1 pc13?0 ? pc13?8 + (ea) 0 1 1 0 0 0 0 0 first byte condition * jr # im 0 0 0 1 a3 a2 a1 a0 pc ? pc+2 to pc+16 0 0 0 0 a3 a2 a1 a0 pc ? pc?1 to pc?15
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 59 jr ? ? jump relative (very short) jr (continued) examples: 1. a short form for a relative jump to label 'kk' is the instruction jr kk where 'kk' must be within the allowed range of current pc?15 to current pc+16. the jr instruction has in this case the effect of an unconditional jp instruction. 2. in the following instruction sequence, if the instruction 'ld wx, #02h' were to be executed in place of 'ld wx,#00h', the program would jump to 1002h and ' jps bbb' would be executed. if 'ld ea,#04h' were to be executed, the jump would be to1004h and ' jps ccc' would be executed. org 1000h jps aaa jps bbb jps ccc jps ddd ld wx,#00h ; wx ? 00h ld ea,wx ads wx,ea ; wx ? (wx) + (wx) jr @wx ; current pc13 ?8 (10h) + wx (00h) = 1000h ; jump to address 1000h and execute jps aaa 3. here is another example: org 1100h ld a,#0h ld a,#1h ld a,#2h ld a,#3h ld 30h,a ; address 30h ? a jps yyy xxx ld ea,#00h ; ea ? 00h jr @ea ; jump to address 1100h ; address 30h ? 00h if 'ld ea,#01h' were to be executed in place of 'ld ea,#00h', the program would jump to 1001h and address 30h would contain the value 1h. if 'ld ea,#02h' were to be executed, the jump would be to 1002h and address 30h would contain the value 2h.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 60 ld ? ? load ld dst,src operation: operand operation summary bytes cycles a,#im load 4-bit immediate data to a 1 1 a,@rra load indirect data memory contents to a 1 1 a,da load direct data memory contents to a 2 2 a,ra load register contents to a 2 2 ra,#im load 4-bit immediate data to register 2 2 rr,#imm load 8-bit immediate data to register 2 2 da,a load contents of a to direct data memory 2 2 ra,a load contents of a to register 2 2 ea,@hl load indirect data memory contents to ea 2 2 ea,da load direct data memory contents to ea 2 2 ea,rrb load register contents to ea 2 2 @hl,a load contents of a to indirect data memory 1 1 da,ea load contents of ea to data memory 2 2 rrb,ea load contents of ea to register 2 2 @hl,ea load contents of ea to indirect data memory 2 2 description: the contents of the source are loaded into the destination. the source's contents are unaffected.if an instruction such as 'ld a,#im' (ld ea,#imm) or 'ld hl,#imm' is written more than two times in succession, only the first ld will be executed; the other similar instructions that immediately follow the first ld will be treated like a nop. this is called the 'redundancy effect' (see examples below). operand binary code operation notation a,#im 1 0 1 1 d3 d2 d1 d0 a ? im a,@rra 1 0 0 0 1 i2 i1 i0 a ? ( rra) a,da 1 0 0 0 1 1 0 0 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 1 1 0 1 1 1 0 1 a ? ra 0 0 0 0 1 r2 r1 r0 ra,#im 1 1 0 1 1 0 0 1 ra ? im d3 d2 d1 d0 1 r2 r1 r0
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 61 ld ? ? load ld (continued) description: operand binary code operation notation rr,#imm 1 0 0 0 0 r2 r1 1 rr ? imm d7 d6 d5 d4 d3 d2 d1 d0 da,a 1 0 0 0 1 0 0 1 da ? a a7 a6 a5 a4 a3 a2 a1 a0 ra,a 1 1 0 1 1 1 0 1 ra ? a 0 0 0 0 0 r2 r1 r0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 1 0 0 0 ea,da 1 1 0 0 1 1 1 0 a ? da, e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 1 1 r2 r1 0 @hl,a 1 1 0 0 0 1 0 0 (hl) ? a da,ea 1 1 0 0 1 1 0 1 da ? a, da + 1 ? e a7 a6 a5 a4 a3 a2 a1 a0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? ea 1 1 1 1 0 r2 r1 0 @hl,ea 1 1 0 1 1 1 0 0 (hl) ? a, (hl + 1) ? e 0 0 0 0 0 0 0 0 examples: 1. ram location 30h contains the value 4h. the ram location values are 40h, 41h and 0ah, 3h respectively. the following instruction sequence leaves the value 40h in point pair hl, 0ah in the accumulator and in ram location 40h, and 3h in register e. ld hl,#30h ; hl ? 30h ld a,@hl ; a ? 4h ld hl,#40h ; hl ? 40h ld ea,@hl ; a ? 0ah, e ? 3h ld @hl,a ; ram (40h) ? 0ah
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 62 ld ? ? load ld (continued) examples: 2. if an instruction such as ld a,#im (ld ea,#imm) or ld hl,#imm is written more than two times in succession, only the first ld is executed; the next instructions are treated as nops. here are two examples of this 'redundancy effect': ld a,#1h ; a ? 1h ld ea,#2h ; nop ld a,#3h ; nop ld 23h,a ; (23h) ? 1h ld hl,#10h ; hl ? 10h ld hl,#20h ; nop ld a,#3h ; a ? 3h ld ea,#35 ; nop ld @hl,a ; (10h) ? 3h the following table contains descriptions of special characteristics of the ld instruction when used in different addressing modes: instruction operation description and guidelines ld a,#im because the 'redundancy effect' occurs with instructions like ld ea,#imm, if this instruction is used consecutively, the second and additional instructions of the same type will be treated like nops. ld a,@rra load the data memory contents pointed to by 8-bit rra register pairs (hl, wx, wl) to the a register. ld a,da load direct data memory contents to the a register. ld a,ra load 4-bit register ra (e, l, h, x, w, z, y) to the a register. ld ra,#im load 4-bit immediate data into the ra register (e, l, h, x, w, y, z). ld rr,#imm load 8-bit immediate data into the ra register (ea, hl, wx, yz). there is a redundancy effect if the operation addresses the hl or ea registers. ld da,a load contents of register a to direct data memory address. ld ra,a load contents of register a to 4-bit ra register (e, l, h, x, w, z, y).
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 63 ld ? ? load ld (concluded) examples: instruction operation description and guidelines ld ea,@hl load data memory contents pointed to by 8-bit register hl to the a register, and the contents of hl+1 to the e register. the contents of register l must be an even number. if the number is odd, the lsb of register l is recognized as a logic zero (an even number), and it is not replaced with the true value. for example, 'ld hl,#36h' loads immediate 36h to hl and the next instruction 'ld ea,@hl' loads the contents of 36h to register a and the contents of 37h to register e. ld ea,da load direct data memory contents of da to the a register, and the next direct data memory contents of da + 1 to the e register. the da value must be an even number. if it is an odd number, the lsb of da is recognized as a logic zero (an even number), and it is not replaced with the true value. for example, 'ld ea,37h' loads the contents of 36h to the a register and the contents of 37h to the e register. ld ea,rrb load 8-bit rrb register (hl, wx, yz) to the ea register. h, w, and y register values are loaded into the e register, and the l, x, and z values into the a register. ld @hl,a load a register contents to data memory location pointed to by the 8-bit hl register value. ld da,ea load the a register contents to direct data memory and the e register contents to the next direct data memory location. the da value must be an even number. if it is an odd number, the lsb of the da value is recognized as logic zero (an even number), and is not replaced with the true value. ld rrb,ea load contents of ea to the 8-bit rrb register (hl, wx, yz). the e register is loaded into the h, w, and y register and the a register into the l, x, and z register. ld @hl,ea load the a register to data memory location pointed to by the 8-bit hl register, and the e register contents to the next location, hl + 1. the contents of the l register must be an even number. if the number is odd, the lsb of the l register is recognized as logic zero (an even number), and is not replaced with the true value. for example, 'ld hl,#36h' loads immediate 36h to register hl; the instruction 'ld @hl,ea' loads the contents of a into address 36h and the contents of e into address 37h.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 64 ldb ? ? load bit ldb dst,src.b ldb dst.b,src operation: operand operation summary bytes cycles mema.b,c load carry bit to a specified memory bit 2 2 memb.@l,c load carry bit to a specified indirect memory bit 2 2 @ h+da.b,c 2 2 c,mema.b load memory bit to a specified carry bit 2 2 c,memb.@l load indirect memory bit to a specified carry bit 2 2 c,@h+da.b 2 2 description: the boolean variable indicated by the first or second operand is copied into the location specified by the second or first operand. one of the operands must be the carry flag; the other can be any directly or indirectly addressable bit. the source is unaffected. operand binary code operation notation mema.b,c * 1 1 1 1 1 1 0 0 mema.b ? c memb.@l,c 1 1 1 1 1 1 0 0 memb.7?2 + [l.3?2]. [l.1?0] ? c 0 1 0 0 a5 a4 a3 a2 @ h+da.b,c 1 1 1 1 1 1 0 0 h + [da.3?0].b ? (c) 0 b2 b1 b0 a3 a2 a1 a0 c,mema.b* 1 1 1 1 0 1 0 0 c ? mema.b c,memb.@l 1 1 1 1 0 1 0 0 c ? memb.7?2 + [l.3?2] . [l.1?0] 0 1 0 0 a5 a4 a3 a2 c,@h+da.b 1 1 1 1 0 1 0 0 c ? [h + da.3?0].b 0 b2 b1 b0 a3 a2 a1 a0 second byte bit addresses * mema.b 1 0 b1 b0 a3 a2 a1 a0 fb0h?fbfh 1 1 b1 b0 a3 a2 a1 a0 ff0h?fffh
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 65 ldb ? ? load bit ldb (continued) examples: 1. the carry flag is set and the data value at input pin p1.0 is logic zero. the following instruction clears the carry flag to logic zero. ldb c,p1.0 2. the p1 address is ff1h and the l register contains the value 9h (1001b). the address (memb.7?2) is 111100b and (l.3?2) is 10b. the resulting address is 11110010b or ff2h and p2 is addressed. the bit value (l.1?0) is specified as 01b (bit 1). ld l,#9h ldb c,p1.@l ; p1.@l specifies p2.1 and c ? p2.1 3. the h register contains the value 2h and flag = 20h.3. the address for h is 0010b and for flag(3?0) the address is 0000b. the resulting address is 00100000b or 20h. the bit value is 3. therefore, @h+flag = 20h.3. flag equ 20h.3 ld h,#2h ldb c,@h+flag ; c ? flag (20h.3) 4. the following instruction sequence sets the carry flag and the loads the "1" data value to the output pin p2.0, setting it to output mode: scf ; c ? "1" ldb p2.0,c ; p2.0 ? "1" 5. the p1 address is ff1h and l = 9h (1001b). the address (memb.7 ?2) is 111100b and (l.3?2) is 10b. the resulting address, 11110010b specifies p2. the bit value (l.1?0) is specified as 01b (bit 1). therefore, p1.@l = p2.1. scf ; c ? "1" ld l,#9h ldb p1.@l,c ; p1.@l specifies p2.1 ; p2.1 ? "1" 6. in this example, h = 2h and flag = 20h.3 and the address 20h is specified. because the bit value is 3, @h+flag = 20h.3: flag equ 20h.3 rcf ; c ? "0" ld h,#2h ldb@h+flag,c ; flag(20h.3) ? "0" note port pin names used in examples 4 and 5 may vary with different sam47 devices.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 66 ldc ? ? load code byte ldc dst,src operation: operand operation summary bytes cycles ea,@wx load code byte from wx to ea 1 3 ea,@ea load code byte from ea to ea 1 3 description: this instruction is used to load a byte from program memory into an extended accumulator. the address of the byte fetched is the five highest bit values in the program counter and the contents of an 8-bit working register (either wx or ea). the contents of the source are unaffected. operand binary code operation notation ea,@wx 1 1 0 0 1 1 0 0 ea ? [pc13?8 + (wx)] ea,@ea 1 1 0 0 1 0 0 0 ea ? [pc13?8 + (ea)] examples: 1. the following instructions will load one of four values defined by the define byte ( db) directive to the extended accumulator: ld ea,#00h call display jps main org 0500h db 66h db 77h db 88h db 99h ? ? ? display ldc ea,@ea ; ea ? address 0500h = 66h ret if the instruction 'ld ea,#01h' is executed in place of 'ld ea,#00h', the content of 0501h (77h) is loaded to the ea register. if 'ld ea,#02h' is executed, the content of address 0502h (88h) is loaded to ea.
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 67 ldc ? ? load code byte ldc (continued) examples: 2. the following instructions will load one of four values defined by the define byte ( db) directive to the extended accumulator: org 0500 db 66h db 77h db 88h db 99h ? ? ? display ld wx,#00h ldc ea,@wx ; ea ? address 0500h = 66h ret if the instruction 'ld wx,#01h' is executed in place of 'ld wx,#00h', then ea ? address 0501h = 77h. if the instruction 'ld wx,#02h' is executed in place of 'ld wx,#00h', then ea ? address 0502h = 88h. 3. normally, the ldc ea, @ea and the ldc ea, @wx instructions reference the table data on the page on which the instruction is located. if, however, the instruction is located at address xxffh, it will reference table data on the next page. in this example, the upper 4 bits of the address at location 0200h is loaded into register e and the lower 4 bits into register a: org 01fdh 01fdh ld wx,#00h 01ffh ldc ea,@wx ; e ? upper 4 bits of 0200h address ; a ? lower 4 bits of 0200h address 4. h ere is another example of page referencing with the ldc instruction: org 0100 db 67h smb 0 ld hl,#30h ; even number ld wx,#00h ldc ea,@wx ; e ? upper 4 bits of 0100h address ; a ? lower 4 bits of 0100h address ld @hl,ea ; ram (30h) ? 7, ram (31h) ? 6
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 68 ldd ? ? load data memory and decrement ldd dst operation: operand operation summary bytes cycles a,@hl load indirect data memory contents to a; decrement register l contents and skip on borrow 1 2 + s description: the contents of a data memory location are loaded into the accumulator, and the contents of the register l are decremented by one. if a "borrow" occurs (e.g., if the resulting value in register l is 0fh), the next instruction is skipped. the contents of data memory and the carry flag value are not affected. operand binary code operation notation a,@hl 1 0 0 0 1 0 1 1 a ? (hl), then l ? l?1; skip if l = 0fh example: in this example, assume that register pair hl contains 20h and internal ram location 20h contains the value 0fh: ld hl,#20h ldd a,@hl ; a ? (hl) and l ? l?1 jps xxx ; skip jps yyy ; h ? 2h and l ? 0fh the instruction ' jps xxx' is skipped because a "borrow" occurred after the 'ldd a,@hl' and instruction ' jps yyy' is executed.
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 69 ldi ? ? load data memory and increment ldi dst,src operation: operand operation summary bytes cycles a,@hl load indirect data memory to a; increment register l contents and skip on overflow 1 2 + s description: the contents of a data memory location are loaded into the accumulator, and the contents of the register l are incremented by one. if an overflow occurs (e.g., if the resulting value in register l is 0h), the next instruction is skipped. the contents of data memory and the carry flag value are not affected. operand binary code operation notation a,@hl 1 0 0 0 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h example: assume that register pair hl contains the address 2fh and internal ram location 2fh contains the value 0fh: ld hl,#2fh ldi a,@hl ; a ? (hl) and l ? l+1 jps xxx ; skip jps yyy ; h ? 2h and l ? 0h the instruction ' jps xxx' is skipped because an overflow occurred after the 'ldi a,@hl' and the instruction ' jps yyy' is executed.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 70 nop ? ? no operation nop operation: operand operation summary bytes cycles ? no operation 1 1 description: no operation is performed by a nop instruction. it is typically used for timing delays. one nop causes a 1-cycle delay: with a 1- s cycle time, five nops would therefore cause a 5- s delay. program execution continues with the instruction immediately following the nop. only the pc is affected. at least three nop instructions should follow a stop or idle instruction. operand binary code operation notation ? 1 0 1 0 0 0 0 0 no operation example: three nop instructions follow the stop instruction to provide a short interval for clock stabilization before power-down mode is initiated: stop nop nop nop
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 71 or ? ? logical or or dst,src operation: operand operation summary bytes cycles a, # im logical-or immediate data to a 2 2 a, @hl logical-or indirect data memory contents to a 1 1 ea,rr logical-or double register to ea 2 2 rrb,ea logical-or ea to double register 2 2 description: the source operand is logically ored with the destination operand. the result is stored in the destination. the contents of the source are unaffected. operand binary code operation notation a, # im 1 1 0 1 1 1 0 1 a ? a or im 0 0 1 0 d3 d2 d1 d0 a, @hl 0 0 1 1 1 0 1 0 a ? a or (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea or rr 0 0 1 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb or ea 0 0 1 0 0 r2 r1 0 example: if the accumulator contains the value 0c3h (11000011b) and register pair hl the value 55h (01010101b), the instruction or ea,@hl leaves the value 0d7h (11010111b) in the accumulator .
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 72 pop ? ? pop f rom stack pop dst operation: operand operation summary bytes cycles rr pop to register pair from stack 1 1 sb pop smb and srb values from stack 2 2 description: the contents of the ram location addressed by the stack pointer is read, and the sp is incremented by two. the value read is then transferred to the variable indicated by the destination operand. operand binary code operation notation rr 0 0 1 0 1 r2 r1 0 rr l ? (sp), rr h ? (sp+1) sp ? sp+2 sb 1 1 0 1 1 1 0 1 (srb) ? (sp), smb ? (sp+1), sp ? sp+2 0 1 1 0 0 1 1 0 example: the sp value is equal to 0edh, and ram locations 0efh through 0edh contain the values 2h, 3h, and 4h, respectively. the instruction pop hl leaves the stack pointer set to 0efh and the data pointer pair hl set to 34h.
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 73 push ? ? push o nto stack push src operation: operand operation summary bytes cycles rr push register pair onto stack 1 1 sb push smb and srb values onto stack 2 2 description: the sp is then decremented by two and the contents of the source operand are copied into the ram location addressed by the stack pointer, thereby adding a new element to the top of the stack. operand binary code operation notation rr 0 0 1 0 1 r2 r1 1 (sp?1) ? rr h , (sp?2) ? rr l sp ? sp?2 sb 1 1 0 1 1 1 0 1 (sp?1) ? smb, (sp?2) ? srb; (sp) ? sp?2 0 1 1 0 0 1 1 1 example: as an interrupt service routine begins, the stack pointer contains the value 0fah and the data pointer register pair hl contains the value 20h. the instruction push hl leaves the stack pointer set to 0f8h and stores the values 2h and 0h in ram locations 0f9h and 0f8h, respectively.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 74 rcf ? ? reset carry flag rcf operation: operand operation summary bytes cycles ? reset carry flag to logic zero 1 1 description: the carry flag is cleared to logic zero, regardless of its previous value. operand binary code operation notation ? 1 1 1 0 0 1 1 0 c ? 0 example: assuming the carry flag is set to logic one, the instruction rcf resets (clears) the carry flag to logic zero.
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 75 ref ? ? reference instruction ref dst operation: operand operation summary bytes cycles memc reference code 1 3 * * the ref in struction for a 16k call instruction is 4 cycles. description: the ref instruction is used to rewrite into 1-byte form, arbitrary 2-byte or 3-byte instructions (or two 1-byte instructions) stored in the ref instruction reference area in program memory. ref reduces the number of program memory accesses for a program. operand binary code operation notation memc t7 t6 t5 t4 t3 t2 t1 t0 pc13?0 = memc7?4, memc3?0 <1 tjp and tcall are 2-byte pseudo-instructions that are used only to specify the reference area: 1. when the reference area is specified by the tjp instruction, memc.7 ?6 = 00 p11 ?0 ? memc.3?0 + ( memc + 1) 2. when the reference area is specified by the tcall instruction, memc.7 ?6 = 01 (sp ?4) (sp?1) (sp?2) ? pc11?0 sp ?3 ? emb, erb, 0, 0 pc11 ?0 ? memc.3?0 + ( memc + 1) sp ? sp?4 when the reference area is specified by any other instruction, the ' memc' and ' memc + 1' instructions are executed. instructions referenced by ref occupy two bytes of memory space (for two 1-byte instructions or one 2-byte instruction) and must be written as an even number from 0020h to 007fh in rom. in addition, the destination address of the tjp and tcall instructions must be located with the 3fffh address. tjp and tcall are reference instructions for jp/jps and call/calls. if the instruction following a ref is subject to the 'redundancy effect', the redundant instruction is skipped. if, however, the ref follows a redundant instruction, it is executed. on the other hand, the binary code of a ref instruction is 1 byte. the upper four bits become the higher address bits of the referenced instruction, and the lower four bits of the referenced instruction ( x 1/2) becomes the lower address, producing a total of 8 bits or 1 byte (see example 3 below).
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 76 ref ? ? reference instruction ref (continued) examples: 1. instructions can be executed efficiently using ref, as shown in the following example: org 0020h aaa ld hl,#00h bbb ld ea,#ffh ccc tcall sub1 ddd tjp sub2 ? ? ? org 0080h ref aaa ; ld hl,#00h ref bbb ; ld ea,#f fh ref ccc ; call sub1 ref ddd ; jp sub2 2. the following example shows how the ref instruction is executed in relation to ld instructions that have a 'redundancy effect': org 0020h aaa ld ea,#40h ? ? ? org 0100h ld ea,#30h ref aaa ; not skipped ? ? ? ref aaa ld ea,#50h ; skipped srb 2
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 77 ref ? ? reference instruction ref (concluded) examples: 3. in this example the binary code of 'ref a1' at locations 20h ?21h is 20h, for 'ref a2' at locations 22h ?23h, it is 21h, and for 'ref a3' at 24h?25h, the binary code is 22h : opcode symbol instruction org 0020h ; 83 00 a1 ld hl,#00h 83 03 a2 ld hl,#03h 83 05 a3 ld hl,#05h 83 10 a4 ld hl,#10h 83 26 a5 ld hl,#26h 83 08 a6 ld hl,#08h 83 0f a7 ld hl,#0fh 83 f0 a8 ld hl,#0f0h 83 67 a9 ld hl,#067h 41 0b a10 tcall sub1 01 0d a11 tjp sub2 ? ? ? org 0100h ; 20 ref a1 ; ld hl,#00h 21 ref a2 ; ld hl,#03h 22 ref a3 ; ld hl,#05h 23 ref a4 ; ld hl,#10h 24 ref a5 ; ld hl,#26h 25 ref a6 ; ld hl,#08h 26 ref a7 ; ld hl,#0fh 27 ref a8 ; ld hl,#0f0h 30 r ef a9 ; ld hl,#067h 31 ref a10 ; call sub1 32 ref a11 ; jp sub2
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 78 ret ? ? return f rom subroutine ret operation: operand operation summary bytes cycles ? return from subroutine 1 3 description: ret pops the pc values successively from the stack, incrementing the stack pointer by six. program execution continues from the resulting address, generally the instruction immediately following a call or calls. operand binary code operation notation ? 1 1 0 0 0 1 0 1 pc13?8 ? (sp+1) (sp) pc7?0 ? (sp+2) (sp+3) psw ? emb,erb sp ? sp+6 example: the stack pointer contains the value 0fah. ram locations 0fah, 0fbh, 0fch, and and 0fdh contain 1h, 0h, 5h, and 2h, respectively. the instruction ret leaves the stack pointer with the new value of 00h and program execution continues from location 0125h. during a return from subroutine, pc values are popped from stack locations as follows: sp ? pc11 ? pc8 sp + 1 0 0 pc13 ? pc12 sp + 2 pc3 ? pc0 sp + 3 pc7 ? pc4 sp + 4 0 0 emb erb sp + 5 0 0 0 0 sp + 6
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 79 rrc ? ? rotate a ccumulator right t hrough carry rrc a operation: operand operation summary bytes cycles a rotate right through carry bit 1 1 description: the four bits in the accumulator and the carry flag are together rotated one bit to the right. bit 0 moves into the carry flag and the original carry value moves into the bit 3 accumulator position. c 3 0 operand binary code operation notation a 1 0 0 0 1 0 0 0 c ? a.0, a3 ? c a.n?1 ? a.n (n = 1, 2, 3) example: the accumulator contains the value 5h (0101b) and the carry flag is cleared to logic zero. the instruction rrc a leaves the accumulator with the value 2h (0010b) and the carry flag is set to logic one.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 80 sbc ? ? subtract w ith carry sbc dst,src operation: operand operation summary bytes cycles a,@hl subtract indirect data memory from a with carry 1 1 ea,rr subtract register pair (rr) from ea with carry 2 2 rrb,ea subtract ea from register pair ( rrb) with carry 2 2 description: sbc subtracts the source and carry flag value from the destination operand, leaving the result in the destination. sbc sets the carry flag if a borrow is needed for the most significant bit; otherwise it clears the carry flag. the contents of the source are unaffected. if the carry flag was set before the sbc instruction was executed, a borrow was needed for the previous step in multiple precision subtraction. in this case, the carry bit is subtracted from the destination along with the source operand. operand binary code operation notation a,@hl 0 0 1 1 1 1 0 0 c,a ? a ? (hl) ? c ea,rr 1 1 0 1 1 1 0 0 c, ea ? ea ?rr ? c 1 1 0 0 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 c,rrb ? rrb ? ea ? c 1 1 0 0 0 r2 r1 0 examples: 1. the extended accumulator contains the value 0c3h, register pair hl the value 0aah, and the carry flag is set to "1": scf ; c ? "1" sbc ea,hl ; ea ? 0c3h ? 0aah ? 1h, c ? "0" jps xxx ; jump to xxx; no skip after sbc 2. if the extended accumulator contains the va lue 0c3h, register pair hl the value 0aah, and the carry flag is cleared to "0": rcf ; c ? "0" sbc ea,hl ; ea ? 0c3h ? 0aah ? 0h = 19h, c ? "0" jps xxx ; jump to xxx; no skip after sbc
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 81 sbc ? ? subtract w ith carry sbc (continued) examples: 3. if sbc a,@hl is followed by an ads a,#im, the sbc skips on 'no borrow' to the instruction immediately after the ads. an 'ads a,#im' instruction immediately after the 'sbc a,@hl' instruction does not skip even if an overflow occurs. this f unction is useful for decimal adjustment operations. a. 8 ? 6 decimal addition (the contents of the address specified by the hl register is 6h): rcf ; c ? "0" ld a,#8h ; a ? 8h sbc a,@hl ; a ? 8h ? 6h ? c(0) = 2h, c ? "0" ads a,#0ah ; skip this instruction because no borrow after sbc result jps xxx b. 3 ? 4 decimal addition (the contents of the address specified by the hl register is 4h): rcf ; c ? "0" ld a,#3h ; a ? 3h sbc a,@hl ; a ? 3h ? 4h ? c(0) = 0fh, c ? "1" ads a,#0ah ; no skip. a ? 0fh + 0ah = 9h ; (the skip function of 'ads a,#im' is inhibited after a ; 'sbc a,@hl' instruction even if an overflow occurs.) jps xxx
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 82 sbs ? ? subtract sbs dst,src operation: operand operation summary bytes cycles a,@hl subtract indirect data memory from a; skip on borrow 1 1 + s ea,rr subtract register pair (rr) from ea; skip on borrow 2 2 + s rrb,ea subtract ea from register pair ( rrb); skip on borrow 2 2 + s description: the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. a skip is executed if a borrow occurs. the value of the carry flag is not affected. operand binary code operation notation a,@hl 0 0 1 1 1 1 0 1 a ? a ? (hl); skip on borrow ea,rr 1 1 0 1 1 1 0 0 ea ? ea ? rr; skip on borrow 1 0 1 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb ? ea; skip on borrow 1 0 1 1 0 r2 r1 0 examples: 1. the accumulator contains the value 0c3h, registe r pair hl contains the value 0c7h, and the carry flag is cleared to logic zero: rcf ; c ? "0" sbs ea,hl ; ea ? 0c3h ? 0c7h, c ? "0" ; sbs instruction skips on borrow, ; but carry flag value is not affected jps xxx ; skip because a borrow occurred jps yyy ; jump to yyy is executed 2. the accumulator contains the value 0afh, register pair hl contains the value 0aah, and the carry flag is set to logic one: scf ; c ? "1" sbs ea,hl ; ea ? 0afh ? 0aah, c ? "1" jps xxx ; jump to xxx ; jps was not skipped because no "borrow" occurred after sbs
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 83 scf ? ? set carry flag scf operation: operand operation summary bytes cycles ? set carry flag to logic one 1 1 description: the scf instruction sets the carry flag to logic one, regardless of its previous value. operand binary code operation notation ? 1 1 1 0 0 1 1 1 c ? 1 example: if the carry flag is cleared to logic zero, the instruction scf sets the carry flag to logic one.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 84 smb ? ? select memory bank smb n operation: operand operation summary bytes cycles n select memory bank 2 2 description: the smb instruction sets the upper four bits of a 12-bit data memory address to select a specific memory bank. the constants 0, 1, and 15 are usually used as the smb operand to select the corresponding memory bank. all references to data memory addresses fall within the following address ranges: please note that because data memory spaces differ for various devices in the sam47 product family, the 'n' value of the smb instruction will also vary. addresses register areas bank smb 000h?01fh working registers 0 0 020h?0ffh stack and general-purpose registers 100h?1dfh general-purpose registers 1 1 1e0h?1ffh display registers f80h?fffh i/o-mapped hardware registers 15 15 the enable memory bank (emb) flag must always be set to "1" in order for the smb instruction to execute successfully for memory banks 0, 1, and 15. format binary code operation notation n 1 1 0 1 1 1 0 1 smb ? n (n = 0, 1, 15) 0 1 0 0 d3 d2 d1 d0 example: if the emb flag is set, the instruction smb 0 selects the data memory address range for bank 0 (000h?0ffh) as the working memory bank.
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 85 srb ? ? select register bank srb n operation: operand operation summary bytes cycles n select register bank 2 2 description: the srb instruction selects one of four register banks in the working register memory area. the constant value used with srb is 0, 1, 2, or 3. the following table shows the effect of srb settings: erb setting srb settings selected register bank 3 2 1 0 0 0 0 x x always set to bank 0 0 0 bank 0 1 0 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 note : 'x' means don't care. the enable register bank flag (erb) must always be set for the srb instruction to execute successfully for register banks 0, 1, 2, and 3. in addition, if the erb value is logic zero, register bank 0 is always selected, regardless of the srb value. operand binary code operation notation n 1 1 0 1 1 1 0 1 srb ? n (n = 0, 1, 2, 3) 0 1 0 1 0 0 d1 d0 example: if the erb flag is set, the instruction srb 3 selects register bank 3 (018h?01fh) as the working memory register bank.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 86 sret ? ? return f rom subroutine and skip sret operation: operand operation summary bytes cycles ? return from subroutine and skip 1 3 + s description: sret is normally used to return to the previously executing procedure at the end of a subroutine that was initiated by a call or calls instruction. sret skips the resulting address, which is generally the instruction immediately after the point at which the subroutine was called. then, program execution continues from the resulting address and the contents of the location addressed by the stack pointer are popped into the program counter. operand binary code operation notation ? 1 1 1 0 0 1 0 1 pc13?8 ? (sp + 1) (sp) pc7?0 ? (sp + 3) (sp + 2) emb,erb ? (sp + 5) (sp + 4) sp ? sp + 6 example: if the stack pointer contains the value 0fah and ram locations 0fah, 0fbh, 0fch, and 0fdh contain the values 1h, 0h, 5h, and 2h, respectively, the instruction sret leaves the stack pointer with the value 00h and the program returns to continue execution at location 0125h. during a return from subroutine, data is popped from the stack to the pc as follows: sp ? pc11 ? pc8 sp + 1 0 0 pc13 ? pc12 sp + 2 pc3 ? pc0 sp + 3 pc7 ? pc4 sp + 4 0 0 emb erb sp + 5 0 0 0 0 sp + 6
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 87 stop ? ? stop operation stop operation: operand operation summary bytes cycles ? engage cpu stop mode 2 2 description: the stop instruction stops the system clock by setting bit 3 of the power control register (pcon) to logic one. when stop executes, all system operations are halted with the exception of some peripheral hardware with special power-down mode operating conditions. in application programs, a stop instruction should be immediately followed by at least three nop instructions. this ensures an adequate time interval for the clock to stabilize before the next instruction is executed. operand binary code operation notation ? 1 1 1 1 1 1 1 1 pcon.3 ? 1 1 0 1 1 0 0 1 1 example: given that bit 3 of the pcon register is cleared to logic zero, and all systems are operational, the instruction sequence stop nop nop nop sets bit 3 of the pcon register to logic one, stopping all controller operations (with the exception of some peripheral hardware). the three nop instructions provide the necessary timing delay for clock stabilization before the next instruction in the program sequence is executed.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 88 vent ? ? load emb, erb, and vector address ventn dst operation: operand operation summary bytes cycles emb (0,1) erb (0,1) adr load enable memory bank flag (emb) and the enable register bank flag (erb) and program counter to vector address, then branch to the corresponding location. 2 2 description: the vent instruction loads the contents of the enable memory bank flag (emb) and enable register bank flag (erb) into the respective vector addresses. it then points the interrupt service routine to the corresponding branching locations. the program counter is loaded automatically with the respective vector addresses which indicate the starting address of the respective vector interrupt service routines. the emb and erb flags should be modified using vent before the vector interrupts are acknowledged. then, when an interrupt is generated, the emb and erb values of the previous routine are automatically pushed onto the stack and then popped back when the routine is completed. after the return from interrupt (iret) you do not need to set the emb and erb values again. instead, use bitr and bits to clear these values in your program routine. the starting addresses for vector interrupts and reset operations are pointed to by the ventn instruction. these addresses must be stored in rom locations 0000h?3fffh. generally, the ventn instructions are coded starting at location 0000h. the format for vent instructions is as follows: ventn d1,d2,addr emb ? d1 ("0" or "1") erb ? d2 ("0" or "1") pc ? addr (address to branch n = device-specific module address code (n = 0?n) operand binary code operation notation emb (0,1) erb (0,1) adr e m b e r b a13 a12 a11 a10 a9 a8 rom (2 x n) 7?6 ? emb, erb rom (2 x n) 5?4 ? 0, pc13, pc12 rom (2 x n) 3?0 ? pc12?8 rom (2 x n + 1) 7?0 ? pc7?0 (n = 0, 1, 2, 3, 4, 5, 6, 7) a7 a6 a5 a4 a3 a2 a1 a0
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 89 vent ? ? load emb, erb, and vector address ventn (continued) example: the instruction sequence org 0000h vent0 1,0,reset vent1 0,1, intb vent2 0,1,int0 vent3 0,1,ints vent4 0,1,intt0 vent5 0,1,intt1 causes the program sequence to branch to the reset routine labeled 'reset,' setting emb to "1" and erb to "0" when reset is activated. when a basic timer interrupt is generated, vent1 causes the program to branch to the basic timer's interrupt service routine, intb, and to set the emb value to "0" and the erb value to "1". vent2 then branches to int0, vent3 to ints, and so on, setting the appropriate emb and erb values.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 90 xch ? ? exchange a or ea with nibble or byte xch dst,src operation: operand operation summary bytes cycles a,da exchange a and data memory contents 2 2 a,ra exchange a and register ( ra) contents 1 1 a,@rra exchange a and indirect data memory 1 1 ea,da exchange ea and direct data memory contents 2 2 ea,rrb exchange ea and register pair ( rrb) contents 2 2 ea,@hl exchange ea and indirect data memory contents 2 2 description: the instruction xch loads the accumulator with the contents of the indicated destination variable and writes the original contents of the accumulator to the source. operand binary code operation notation a,da 0 1 1 1 1 0 0 1 a ? da a7 a6 a5 a4 a3 a2 a1 a0 a,ra 0 1 1 0 1 r2 r1 r0 a ? ra a,@rra 0 1 1 1 1 i2 i1 i0 a ? ( rra) ea,da 1 1 0 0 1 1 1 1 a ? da,e ? da + 1 a7 a6 a5 a4 a3 a2 a1 a0 ea,rrb 1 1 0 1 1 1 0 0 ea ? rrb 1 1 1 0 0 r2 r1 0 ea,@hl 1 1 0 1 1 1 0 0 a ? (hl), e ? (hl + 1) 0 0 0 0 0 0 0 1 example: double register hl contains the address 20h. the accumulator contains the value 3fh (00111111b) and internal ram location 20h the value 75h (01110101b). the instruction xch ea,@hl leaves ram location 20h with the value 3fh (00111111b) and the extended accumulator with the value 75h (01110101b).
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 91 xchd ? ? exchange and decrement xchd dst,src operation: operand operation summary bytes cycles a,@hl exchange a and data memory contents; decrement contents of register l and skip on borrow 1 2 + s description: the instruction xchd exchanges the contents of the accumulator with the ram location addressed by register pair hl and then decrements the contents of register l. if the content of register l is 0fh, the next instruction is skipped. the value of the carry flag is not affected. operand binary code operation notation a,@hl 0 1 1 1 1 0 1 1 a ? (hl), then l ? l?1; skip if l = 0fh example: register pair hl contains the address 20h and internal ram location 20h contains the value 0fh: ld hl,#20h ld a,#0h xchd a,@hl ; a ? 0fh and l ? l ? 1, (hl) ? "0" jps xxx ; skipped because a borrow occurred jps yyy ; h ? 2h, l ? 0fh yyy xchd a,@hl ; (2fh) ? 0fh, a ? (2fh), l ? l ? 1 = 0eh ? ? ? the ' jps yyy' instruction is executed because a skip occurs after the xchd instruction.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 92 xchi ? ? exchange and increment xchi dst,src operation: operand operation summary bytes cycles a,@hl exchange a and data memory contents; increment contents of register l and skip on overflow 1 2 + s description: the instruction xchi exchanges the contents of the accumulator with the ram location addressed by register pair hl and then increments the contents of register l. if the content of register l is 0h, a skip is executed. the value of the carry flag is not affected. operand binary code operation notation a,@hl 0 1 1 1 1 0 1 0 a ? (hl), then l ? l+1; skip if l = 0h example: register pair hl contains the address 2fh and internal ram location 2fh contains 0fh: ld hl,#2fh ld a,#0h xchi a,@hl ; a ? 0fh and l ? l + 1 = 0, (hl) ? "0" jps xxx ; skipped because an overflow occurred jps yyy ; h ? 2h, l ? 0h yyy xchi a,@hl ; (20h) ? 0fh, a ? (20h), l ? l + 1 = 1h ? ? ? the ' jps yyy' instruction is executed because a skip occurs after the xchi instruction.
ks57c 0502/c0504/p0504 microcontroller instruction set 5 ? 93 xor ? ? logical exclusive or xor dst,src operation: operand operation summary bytes cycles a,#im exclusive-or immediate data to a 2 2 a,@hl exclusive-or indirect data memory to a 1 1 ea,rr exclusive-or register pair (rr) to ea 2 2 rrb,ea exclusive-or register pair ( rrb) to ea 2 2 description: xor performs a bitwise logical xor operation between the source and destination variables and stores the result in the destination. the source contents are unaffected. operand binary code operation notation a,#im 1 1 0 1 1 1 0 1 a ? a xor im 0 0 1 1 d3 d2 d1 d0 a,@hl 0 0 1 1 1 0 1 1 a ? a xor (hl) ea,rr 1 1 0 1 1 1 0 0 ea ? ea xor (rr) 0 0 1 1 1 r2 r1 0 rrb,ea 1 1 0 1 1 1 0 0 rrb ? rrb xor ea 0 0 1 1 0 r2 r1 0 example: if the extended accumulator contains 0c3h (11000011b) and register pair hl contains 55h (01010101b), the instruction xor ea,hl leaves the value 96h (10010110b) in the extended accumulator.
instruction set ks57c 0502/c0504/p0504 microcontroller 5? 94 notes
oscillator circuits interrupts power-down reset i/o ports timers and timer/counter comparator serial i/o interface electrical data mechanical data ks57p0504 otp development tools

ks57c 0502/c0504/p0504 microcontroller oscillator circuit 6? 1 6 oscillator circuits overview the KS57C0502/c0504 has a system clock cir cuit. the cpu and peripheral hardware operate on the system clock frequency supplied through these on-chip circuits. specifically, a clock is required by the following peripheral modules: ? basic timer ? timer/counter 0 ? watch timer ? serial i/o interface ? clock output circuit the system clock frequency can be divided by 4, 8, or 64. by manipulating pcon bits 1 and 0, you can select one of the following frequencies as the cpu clock. fx 4 , fx 8 , fx 64 when the pcon register is cleared to zero after reset , the normal cpu operating mode is enabled, a system clock of fx/64 is selected. bits 3 and 2 of the pcon register can be manipulated by a stop or idle instruction to engage stop or idle power-down mode.
oscillator circuit ks57c 0502/c0504/p0504 microcontroller 6? 2 oscillator stop cpu clock wait release signal internal reset signal power-down release signal pcon.3,2 clear x in x out fx cpu stop signal ( idle mode) idle stop watch timer basic timer timer/counter 0 clock output circit comparator 1/4 oscillator control circuit system oscillator circuit frequency dividing circuit 1/2 1/16 selector pcon.0 pcon.1 pcon.2 pcon.3 figure 6?1. clock circuit diagram
ks57c 0502/c0504/p0504 microcontroller oscillator circuit 6? 3 system oscillator circuits x in x out figure 6?2. crystal/ceramic oscillator x in x out figure 6?3. external clock
oscillator circuit ks57c 0502/c0504/p0504 microcontroller 6? 4 power control register (pcon) the power control register, pcon, is a 4-bit register that is used to select the cpu clock frequency and to con trol cpu operating and power-down modes. pcon is mapped to ram address fb3h and can be addressed di rectly by 4-bit write instructions or by the instructions idle and stop. fb3h pcon.3 pcon.2 pcon.1 pcon.0 pcon bits 3 and 2 are controlled by the stop and idle instructions to engage the idle and stop power-down modes. idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag (emb). pcon bits 1 and 0 are used to select a specific system clock frequency. reset sets pcon register values to logic zero. pcon.1 and pcon.0 divide the frequency ( fx) by 64, 8, and 4. pcon.3 and pcon.2 enable normal cpu operating mode. table 6?1. power control register (pcon) organization + + programming tip ? setting the cpu clock to set the cpu clock to 0.95 s at 4.19 mhz: bits emb smb 15 ld a,#3h ld pcon,a pcon bit settings resulting cpu operating mode pcon.3 pcon.2 0 0 normal cpu operating mode 0 1 idle power-down mode 1 0 stop power-down mode pcon bit settings resulting cpu clock frequency pcon.1 pcon.0 0 0 fx/64 1 0 fx/8 1 1 fx/4
ks57c 0502/c0504/p0504 microcontroller oscillator circuit 6? 5 instruction cycle times the unit of time that equals one machine cycle varies depending on how the oscillator clock signal is divided (by 4, 8, or 64). table 6?2 shows corresponding cycle times in microseconds. table 6?2. instruction cycle times for cpu clock rates selected cpu clock resulting frequency oscillation source cycle time ( sec) fx/64 65.5 khz 15.3 fx/8 524.0 khz fx = 4.19 mhz 1.91 fx/4 1.05 mhz 0.95 clock output mode register (clmod) the clock output mode register, clmod, is a 4-bit register that is used to enable or disable clock output to the clo pin and to select the cpu clock source and frequency. clmod is mapped to ram address fd0h and is ad - dressable by 4-bit write instructions only. fd0h clmod.3 "0" clmod.1 clmod.0 reset clears clmod to logic zero, which automatically selects the cpu clock as the clock source (without initiating clock oscillation), and disables clock output. clmod.3 is the enable/disable clock output control bit; clmod.1 and clmod.0 are used to select one of four possible clock sources and frequencies: normal cpu clock, fx/8, fx/16, or fx/64. table 6?3. clock output mode register (clmod) organization clmod bit settings resulting clock output clmod.1 clmod.0 clock source frequency 0 0 cpu clock (fx/4, fx/8, fx/64) 1.05 mhz, 524 khz, 65.5 khz 0 1 fx/8 524 khz 1 0 fx/16 262 khz 1 1 fx/64 65.5 khz clmod.3 result of clmod.3 setting 0 clock output is disabled 1 clock output is enabled note : frequencies assume that fx = 4.19 mhz.
oscillator circuit ks57c 0502/c0504/p0504 microcontroller 6? 6 clock output circuit the clock output circuit, used to output clock pulses to the clo pin, has the following components: ? 4-bit clock output mode register (clmod) ? clock selector ? output latch ? port mode flag ? clo output pin (p3.2) clo clocks 4 (fx/8, fx/16, fx/64, cpu clock) clmod.3 clmod.2 clmod.1 clmod.0 pm3.2 p3.2 output latch clock selector figure 6? 4 . clo output pin circuit diagram clock output procedure to output clock pulses to the clo pin, follow this general procedure: 1. disable clock output by clearing clmod.3 to logic zero. 2. set the clock output frequency (clmod.1, clmod.0). 3. load a "0" to the output latch of the clo pin (p3.2). 4. set the p3.2 mode flag (pm3.2) to output mode. 5. enable clock output by setting clmod.3 to logic one. + + programming tip ? cpu clock output to the clo pin to output the cpu clock to the clo pin: bits emb ; or bitr emb smb 15 ld ea,#40h ld pmg1,ea ; p3.2 ? output mode bitr p3.2 ; clear p3.2 output latch ld a,#9h ld clmod,a
ks57c 0502/c0504/p0504 microcontroller interrupts 7? 1 7 interrupts overview KS57C0502/c0504 microcontrollers process three types of interrupts: ? internal interrupts generated by on-chip processes ? external interrupts generated by external peripheral devices ? quasi-interrupts used for edge detection and clock sources table 7?1. interrupts and corresponding i/o pin(s) interrupt type interrupt name i/o port pin(s) external interrupts int0, int1 p1.0, p1.1 internal interrupts intb, intt0, ints not applicable quasi-interrupts intk p6.0?p6.2 (ks0?ks2) intw not applicable the interrupt control circuit has four functional components: ? interrupt enable flags ( iex) ? interrupt request flags ( irqx) ? interrupt priority registers (ime and ipr) ? power-down release signal circuit vectored interrupts interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software. a vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt, are enabled (set to logic one): ? interrupt enable flag ( iex) ? interrupt master enable flag (ime) ? interrupt request flag ( irqx) ? interrupt status flags (is0, is1) ? i nterrupt priority register (ipr) if all conditions are satisfied, the start address of the interrupt is loaded into the program counter and the pro - gram starts executing the service routine from this address.
interrupts ks57c 0502/c0504/p0504 microcontroller 7? 2 vectored interrupts (continued) emb and erb flags for ram memory and register banks are stored in the vector address area of the rom during interrupt service routines. the flags are stored at the beginning of the program with the vent instruction. enable flag values are saved during the main routine, as well as during service routines. any changes you make to enable flag values during a service routine are not stored in the vector address. when an interrupt occurs, the enable flag values before the interrupt is initiated are saved along with the pro - gram status word (psw), and the enable flag values for the interrupt is fetched from the respective vector address. then, if required, you can modify the enable flags during the interrupt service routine. when the interrupt ser - vice routine is returned to the main routine by the iret instruction, however, the original values saved in the stack are restored and the main program continues program execution with these values. software-generated interrupts to generate an interrupt request from software, the program manipulates the appropriate irqx flag. when the interrupt request value in the irqx flag is set, it is retained until all other conditions for the interrupt have been met, and the service routine can be initiated. multiple interrupts by manipulating the two interrupt status flags (is0 and is1), you can control service routine initialization and thereby process multiple interrupts simultaneously. power-down mode release an interrupt (with the exception of int0) can be used to release power-down mode (stop or idle). interrupts for power-down mode release are initiated by setting the corresponding interrupt enable flag. even if the ime flag is cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag has been set. in such cases, the interrupt routine will not be executed since ime = "0".
ks57c 0502/c0504/p0504 microcontroller interrupts 7? 3 request flag (irqx) <-- 1 interrupt is generated (int xx) generate corresponding vector interrupt and release power-down mode high-priority interrupt? is1,0 = 0,0? is1,0 = 0,1 ? store contents of pc and psw in the stack area; set pc contents to corresponding vector address is1,0 = 0,1 reset corresponding irqx flag jump to interrupt start address retain value until interrupt service routine is completed retain value until ime = 1 ime = 1? is1,0 = 1,0 no no no no yes yes yes yes yes no retain value until iex = 1 iex = 1? figure 7?1. interrupt execution flowchart
interrupts ks57c 0502/c0504/p0504 microcontroller 7? 4 irqb irq0 irq1 irqs irqt0 irqw irqk iet0 ies ie1 ie0 ieb imod1 imod0 intb int0 int1 ints intt0 intw # @ @ power-down mode release signal ime ipr is1 is0 interrupt control unit vector interrupt generator # = noise filtering circuit @ = edge detection circuit imodk intk (ks0?ks2) iew iek figure 7?2. interrupt control circuit diagram
ks57c 0502/c0504/p0504 microcontroller interrupts 7? 5 multiple interrupts the interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all inter rupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service routine for a lower-priority request is accepted during the execution of a higher priority routine. two-level interrupt handling two-level interrupt handling is the standard method for processing multiple interrupts. when the is1 and is0 bits of the psw (fb0h.3 and fb0h.2, respectively) are both logic zero, program execution mode is normal and all interrupt requests are serviced. see figure 7?3. whenever an interrupt request is accepted, is1 and is0 are incremented by one ("0" ? "1" or "1" ? "0"), and the values are stored in the stack along with the other psw bits. after the interrupt routine has been serviced, the modified is1 and is0 values are automatically restored from the stack by an iret instruction. is0 and is1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable memory bank flag (emb). before you can modify an interrupt service flag, however, you must first disable interrupt processing with a di instruction. when you set is1 to "0" and is0 to "1", you inhibit all interrupt service routines except for the highest priority in terrupt currently defined by the interrupt priority register (ipr). int disable set ipr int enable low or high level interrupt generated normal program processing (status 0) high-level interrupt generated high or low level interrupt processing (status 1) high level interrupt processing (status 2) figure 7?3. two-level interrupt handling multi-level interrupt handling with multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority inter - rupt is being serviced. this is done by manipulating the interrupt status flags, is0 and is1. see figure 7?4. when an interrupt is requested during normal program execution, the interrupt status flags is0 and is1 are set to "0" and "1", respectively. this setting allows only highest-priority interrupts to be serviced. when a high-priority request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority level can be serviced. in this way, the high-priority and low -priority requests will be serviced in parallel.
interrupts ks57c 0502/c0504/p0504 microcontroller 7? 6 table 7?2. is1 and is0 function process status before int effect of isx bit setting after int ack is1 is0 is1 is0 0 0 0 all interrupt requests are serviced. 0 1 1 0 1 only high-priority interrupts as determined by the current settings in the ipr register are serviced. 1 0 2 1 0 no additional interrupt requests will be serviced. ? ? ? 1 1 value undefined ? ? int disable set ipr int enable low or high level interrupt generated normal program processing (status 0) low or high level interrupt generated single interrupt 2-level interrupt status 1 status 1 status 0 status 0 int enable modify status int disable high-level interrupt generated status 2 3-level interrupt figure 7?4. multiple-level interrupt handling
ks57c 0502/c0504/p0504 microcontroller interrupts 7? 7 interrupt priority register (ipr) the 4-bit interrupt priority register (ipr) is used to control multi-level interrupt handling. the ipr is mapped to ram address fb2h, and its reset value is logic zero. before the ipr can be modified by 4-bit write instructions, all interrupts must first be disabled by a di instruction. fb2h ime ipr.2 ipr.1 ipr.0 by manipulating the ipr settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. interrupt default priority intb 1 int0 2 int1 3 ints 4 intt0 5 the msb of the ipr, the interrupt master enable flag (ime), enables and disables all interrupt process ing. even if an interrupt request flag and its corre sponding enable flag are set, a service routine cannot be executed until the ime flag is set to logic one. the ime flag is mapped to fb2h.3 and can be di rectly manipulated by ei and di instructions, regard less of the current enable memory bank (emb) value. table 7?4. interrupt priority register settings ipr.2 ipr.1 ipr.0 result of ipr bit setting 0 0 0 process all interrupt requests at low priority. 0 0 1 process intb interrupt only. 0 1 0 process int0 interrupts only. 0 1 1 process int1 interrupts only. 1 0 0 process ints interrupts only. 1 0 1 process intt0 interrupts only. note : when all interrupts are low priority (the lower three bits of the ipr register are logic zero), the interrupt generated first will become high priority. therefore, the first generated interrupt cannot be superceded by any other interrupt. if two or more interrupt requests are received simultaneously, the priority level is determined according to the standard interrupt priorities in table 7.4 (e.g., the default priority assigned by hardware when the lower three ipr bits = "0"). in this case, the higher-priority interrupt request is serviced and the other interrupt is inhibited. then, when the high-priority interrupt is returned from its service routine by an iret instruction, the inhibited interrupt service routine is started.
interrupts ks57c 0502/c0504/p0504 microcontroller 7? 8 + + programming tip ? setting the int interrupt priority set the int1 interrupt to high priority: bits emb smb 15 di ; ipr.3 (ime) ? 0 ld a,#3h ld ipr,a ei ; ipr.3 (ime) ? 1 external interrupt mode registers (imod0, imod1) the following components are used to process external interrupts at the int0 and int1 pin: ? noise filtering circuit for int0 ? edge detection circuit ? two mode registers, imod0 and imod1 the mode registers are used to control the triggering edge of the input signal. imod settings let you choose either the rising or falling edge of the incoming signal at the int0 and int1 pins as the interrupt request trigger. fb4h imod0.3 "0" imod0.1 imod0.0 fb5h "0" "0" "0" imod1.0 imod0 and imod1 bits are mapped to ram addresses fb4h (imod0) and fb5h (imod1), and are addressable by 4-bit write instructions. reset clears all imod values to logic zero, selecting rising edges as the trigger for incoming interrupt requests. table 7?5. imod0 and imod1 register organization imod0 imod0.3 0 imod0.1 imod0.0 effect of imod0 settings 0 select cpu clock for sampling 1 select fx/64 sampling clock 0 0 rising edge detection 0 1 falling edge detection 1 0 both rising and falling edge detection 1 1 irq0 flag cannot be set to "1" imod1 0 0 0 imod1.0 effect of imod1 settings 0 rising edge detection 1 falling edge detection
ks57c 0502/c0504/p0504 microcontroller interrupts 7? 9 external interrupt 0 and 1 mode registers (c ontinued ) when a sampling clock rate of fx/64 is used for int0, an interrupt request flag must be cleared before 16 ma - chine cycles have elapsed. since the int0 pin has a clock-driven noise filtering circuit built into it, please take the following precautions when you use it: ? to trigger an interrupt, the input signal width at int0 must be at least two times wider than the pulse width of the clock se lected by imod0. this is true even when the int0 pin is used for ge neral-purpose input. ? since the int0 input sampling clock does not operate during stop or idle mode, you cannot use int0 to re - lease power-down mode. int0 cpu clock fx/64 int1 noise filter edge detection irq0 imod0 imod1 clock selector p1.1 p1.0 edge detection irq1 figure 7?5. circuit diagram for int0 and int1 pins when modifying the imod0 and imod1 registers, it is possible to accidentally set an interrupt request flag. to avoid unwanted interrupts, take these precautions when writing your programs: 1. disable all interrupts with a di instruction. 2. modify the imod0 or imod1 register. 3. clear all relevant interrupt request flags. 4. enable the interrupt by setting the appropriate iex flag. 5. enable all interrupts with an ei instructions.
interrupts ks57c 0502/c0504/p0504 microcontroller 7? 10 key interrupt mode register (imodk) the mode register for external interrupts at the ks0?ks2 pins, imodk, is a 4-bit register at ram address fb6h. imodk is addressable only by 4-bit write instructions. reset clears all imodk bits to logic zero. fb6h "0" imodk.2 imodk.1 imodk.0 when bits in the imodk register are set to logic one, intk uses the falling edge of an incoming signal at corresponding pins as the interrupt request trigger. when a falling edge is detected at any one of the pins ks0? ks2, the irqk flag is set to logic one and a release signal for power-down mode is generated. table 7?6. imodk register bit settings imodk 0 imodk.2 imodk.1 imodk.0 effect of imodk settings 0 0 0 disable key interrupt 0 0 1 select falling edge at ks0 0 1 0 select falling edge at ks1 0 1 1 select falling edge at ks0?ks1 1 0 0 select falling edge at ks2 1 0 1 select falling edge at ks0, ks2 1 1 0 select falling edge at ks1?ks2 1 1 1 select falling edge at ks0?ks2 ks2 ks1 ks0 falling edge detection circuit 1. to generate a key interrupt on a falling edge at ks0?ks2, all ks0?ks2 pins must be configured to input mode. 2. if anyone of the ks0-ks2 pins used for interrupt stays low, a key interrupt is not generated. since all ks0-ks2 pins are anded, the falling edge detection circuit cannot detects a falling edge. notes: irqk imodk figure 7?6. circuit diagram for ks0?ks2 pins
ks57c 0502/c0504/p0504 microcontroller interrupts 7? 11 + + programming tip ? using intk as a key input interrupt when the intk interrupt used as a key interrupt, the key interrupt pin must be set to input. 1. when ks0 ?ks2 are selected: bits emb smb 15 ld a,#3h ld imodk,a ; (imodk) ? #3h, ks0?ks2 falling edge select ld ea,#00h ld pmg3,ea ; p6 ? input mode ld ea,#40h ld pumod,ea ; enable p6 pull-up resistors
interrupts ks57c 0502/c0504/p0504 microcontroller 7? 12 interrupt flags there are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each in - terrupt, the interrupt master enable flag, which enables or disables all interrupt processing. interrupt master enable flag (ime) the interrupt master enable flag, ime, enables or disables all interrupt processing. therefore, even when an irqx flag is set and its corresponding iex flag is enabled, the interrupt service routine is not executed until the ime flag is set to logic one. the ime flag is located in the ipr register (ipr.3), and is mapped to bit address fb2h.3. it can be directly be manipulated by ei and di instructions, regardless of the current value of the enable memory bank flag (emb). interrupt enable flags ( iex) iex flags, when set to logic one, enable specific interrupt requests to be serviced. when the interrupt request flag is set to logic one, an interrupt will not be serviced until its corresponding iex flag is also enabled. interrupt enable flags are mapped to the ram address area fb8h?fbfh, and can be read, written, or tested directly by 1-bit instructions (bits and bitr). iex flags can be addressed directly at their specific ram addresses, despite the current value of the enable memory bank (emb) flag. interrupt request flags ( irqx) interrupt request flags, located in the ram area fb8h-fbfh, are read/write addressable by 1-bit or 4-bit in - structions. irqx flags can be addressed directly at their specific ram addresses, regardless of the current value of the enable memory bank (emb) flag. when a specific irqx lag is set to logic one, the corresponding interrupt request is generated. the flag is then automatically cleared to logic zero by hardware when the interrupt has been serviced. exceptions are the watch timer interrupt request flag, irqw, and key interrupt request flag irqk, which must be cleared by software after the interrupt service routine has executed. irqx flags are also used to execute interrupt requests from software. in summary, follow these guidelines for using irqx flags: 1. irqx is set to request an interrupt when an interrupt meets the set condition for interrupt generation. 2. irqx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the exception of irqw and irq2). 3. when irqx is set to "1" by software, an interrupt is generated.
ks57c 0502/c0504/p0504 microcontroller interrupts 7? 13 interrupt master enable flag (ime) the interrupt master enable flag, ime, inhibits or enables all interrupt processing. therefore, even when an irqx flag and its corresponding iex flag is enabled, an interrupt request will not be serviced until the ime flag is set to logic one. the ime flag is the most significant bit of the 4-bit ipr register at ram location fb2h. ime ipr.2 ipr.1 ipr.0 effect of bit settings 0 inhibit all interrupts 1 enable all interrupts you can manipulate the ime flag using ei and di instructions, despite the current value of the enable memory bank (emb) flag. interrupt enable flags ( ie x ) interrupt enable flags are used to control the execution of service routines for specific interrupt requests. the enable flag has priority over a request flag ? even if the irqx flag is enabled, the interrupt request will not be ser viced until the corresponding iex flag is set to logic one. using 1-bit or 4-bit instructions and direct addressing, you can read, write, or test iex (and irqx) flags despite the current enable memory bank (emb) value. the iex and irqx flags are mapped to ram area fb8h?fbfh. table 7?7. interrupt enable and interrupt request flag addresses address bit 3 bit 2 bit 1 bit 0 fb8h 0 0 ieb irqb fbah 0 0 iew irqw fbbh 0 0 0 0 fbch 0 0 iet0 irqt0 fbdh 0 0 ies irqs fbeh ie1 irq1 ie0 irq0 fbfh 0 0 iek irqk notes: 1. iex refers generically to all interrupt enable flags. 2. irqx refers generically to all interrupt request flags. 3. iex = 0 is interrupt disable mode. 4. iex = 1 is interrupt enable mode.
interrupts ks57c 0502/c0504/p0504 microcontroller 7? 14 interrupt request flags ( irq x ) when an interrupt request flag ( irqx) is set, a software-generated interrupt is enabled for the corresponding in terrupt. irqx flags can be written by 1- or 4-bit ram control instructions. irqx flags are then cleared automatically when the interrupt has been serviced. exceptions to the general rule are the watch timer interrupt request flag, irqw and key interrupt request flag, irqk; they must be cleared by software after the interrupt service routine has executed. table 7?8. interrupt request flag conditions and priorities interrupt source internal / external pre-condition for irqx flag setting interrupt priority irqx flag name intb i reference time interval signal from basic timer 1 irqb int0 e rising or falling edge detected at int0 pin 2 irq0 int1 e rising or falling edge detected at int1 pin 3 irq1 ints i completion signal for serial transmit-and-re - ceive or receive-only operation 4 irqs intt0 i signals for tcnt0 and tref0 registers coin - cide 5 irqt0 intk * e falling edge is detected at any one of the ks0? ks2 pins ? irqk intw * i time interval of 0.5 secs or 3.19 msecs ? irqw * intk and intw are quasi-interrupts and intk is used only for testing incoming signals.
ks57c 0502/c0504/p0504 microcontroller power-down 8? 1 8 power-down overview the KS57C0502/c0504 microcontroller has two power-down modes to reduce power consumption: idle and stop. idle mode is initiated by the idle instruction and stop mode by the instruction stop. (several nop instructions must always follow an idle or stop instruction in a program.) in idle mode, the cpu clock stops while pe ripherals and the oscillation source continue to operate normally. when reset occurs during normal operation or during a power-down mode, a reset operation is initiated and the cpu enters idle mode. when the standard oscillation stabilization time interval (31.3 ms at 4.19 mhz) has elapsed, normal cpu operation resumes. in stop mode, system clock oscillation is halted (assuming it is currently operating), and peripheral hard ware components are powered-down. the effect of stop mode on specific peripheral hardware components ? cpu, basic timer, serial i/o, timer/ counters 0, and watch timer ? and on external interrupt requests, is detailed in table 8?1. note do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. idle or stop modes are terminated either by a reset , or by an interrupt with the exception of int0, which are enabled by the corresponding interrupt enable flag, iex. when power-down mode is terminated by reset input, a normal reset operation is executed. assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down mode is released immediately upon entering power-down mode. when an interrupt is used to release power-down mode, the operation differs depending on the value of the interrupt master enable flag (ime): ? if the ime flag = "0", program execution is started immediately after the instruction which issues the request to enter power-down mode. the interrupt request flag remains set to logic one. ? if the ime flag = "1", two instructions are executed after the power-down mode release. then, the vectored interrupt is initiated. however, when the release signal is caused by intk or intw, the operation is identical to the ime = 0 condition. that is, a vector interrupt is not generated.
power-down ks57c 0502/c0504/p0504 microcontroller 8? 2 table 8?1. hardware operation during power-down modes operation stop mode (stop) idle mode (idle) clock oscillator system clock oscillation stops cpu clock oscillation stops (system clock oscillation continues) basic timer basic timer stops basic timer operates (with irqb set at each reference interval) serial interface operates only if external sck input is selected as the serial i/o clock operates if a clock other than the cpu clock is selected as the serial i/o clock timer/counter 0 operates only if tcl0 is selected as the counter clock timer/counter 0 operates comparator comparator operation is stopped comparator operates watch timer watch timer operation is stopped watch timer operates external interrupts int1 and intk are acknowledged; int0 is not serviced int1 and intk are acknowledged; int0 is not serviced cpu all cpu operations are disabled all cpu operations are disabled power-down mode release signal interrupt request signals (except int0) are enabled by an interrupt enable flag or by reset input interrupt request signals (except int0) are enabled by an interrupt enable flag or by reset input
ks57c 0502/c0504/p0504 microcontroller power-down 8? 3 idle mode timing diagrams clock signal idle instruction oscillation stabilization (31.3 ms / 4.19 mhz) normal mode idle mode normal mode normal oscillation reset figure 8?1. timing when idle mode is released by reset normal mode idle mode normal mode normal oscillation mode release signal idle instruction clock signal interrupt acknowledge (ime = 1) figure 8?2. timing when idle mode is released by an interrupt
power-down ks57c 0502/c0504/p0504 microcontroller 8? 4 stop mode timing diagrams clock signal stop instruction oscillation stabilization (31.3 ms / 4.19 mhz) normal mode idle mode normal mode oscillation resumes stop mode oscillation stops reset figure 8?3. timing when stop mode is released by reset oscillation stabilization (bmod setting) normal mode idle mode normal mode oscillation resumes stop mode oscillation stops mode release signal stop instruction clock signal int ack (ime = 1) figure 8?4. timing when stop mode is release by an interrupt
ks57c 0502/c0504/p0504 microcontroller power-down 8? 5 i/o port pin configuration for power-down the following method describes how to configure i/o port pins to reduce power consumption during power- down modes (stop, idle): condition 1: if the microcontroller is not configured to an external device: 1. connect unused port pins according to the information in table 8 ?2. 2. disable all pull-up resistors for output pins by making the appropriate modifications to the pull-up resistor mode register, pumod. reason: if output goes low when the pull-up resistor is enabled, there may be un - expected surges of current through the pull-up. 3. disable pull-up resistors for input pins configured to v dd or v ss levels in order to check the current input option. reason: if the input level of a port pin is set to v ss when a pull-up resistor is enabled, it will draw an unnecessarily large current. condition 2: if the microcontroller is configured to an external device and the external device's v dd source is turned off in power-down mode. 1. connect unused port pins according to the information in table 8 ?2. 2. disable the pull-up resistors of output pins by making the appropriate modifications to the pull-up resistor mode register, pumod. reason: if output goes low when the pull-up resistor is enabled, there may be un - expected surges of current through the pull-up. 3. disable pull-up resistors for input pins configured to v dd or v ss levels in order to check the current input option. reason: if the input level of a port pin is set to v ss when a pull-up resistor is enabled, it will draw an unnecessarily large current. 4. disable the pull-up resistors of input pins connected to the external device by making the necessary modi - fications to the pumod register. 5. configure the output pins that are connected to the external device to low level. reason: when the exter - nal device's v dd source is turned off, and if the microcontroller's output pins are set to high level, v dd ? 0.7 v is supplied to the v dd of the external device through its input pin. this causes the device to operate at the level v dd ? 0.7 v. in this case, total current consumption would not be reduced. 6. determine the correct output pin state necessary to block current pass in according with the e xternal tran - sistors (pnp, npn).
power-down ks57c 0502/c0504/p0504 microcontroller 8? 6 recommended connections for unused pins to reduce overall power consumption, please configure unused pins according to the guidelines described in table 8?2. table 8?2. unused pin connections for reduced power consumption pin/share pin names recommended connection p0.0 / sck p0.1 / so p0.2 / si input mode: connect to v dd output mode: do not connect p1.0 / int0 ? p1.1 / int1 connect to v dd p2.0 / cin0 p2.1 / cin1 p2.2 / cin2 p2.3 / cin3 connect to v dd p3.0 / tclo0 p3.1 / tclo1 p3.2 / clo p3.3 / buz p4.0?p4.3 p5.0?p5.3 p6.0 / ks0 ? p6.3 / buz input mode: connect to v dd output mode: do not connect
ks57c 0502/c0504/p0504 microcontroller reset 9? 1 9 reset overview when a reset signal is input during normal operation or power-down mode, a reset operation is initiated and the cpu enters idle mode. then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 mhz has elapsed, normal system operation resumes. regardless of when the reset occurs ? during normal operating mode or during power-down mode ? the effect on most hardware register values is almost identical. the exceptions are as follows: ? carry flag ? data memory values ? general-purpose registers e, a, l, h, x, w, z, and y ? serial i/o buffer register (sbuf) if a reset occurs during idle or stop mode, the current values in these registers are retained. otherwise, their values are undefined. oscillation stabilization (31.3 ms / 4.19 mhz) idle mode operating mode reset input normal mode or power-down mode reset operation figure 9?1. timing for oscillation stabilization after reset hardware register values after reset table 9?1 gives you detailed information about hardware register values after a reset occurs during power- down mode or during normal operation.
reset ks57c 0502/c0504/p0504 microcontroller 9? 2 table 9 - 1. hardware register values after reset hardware component or subcomponent if reset occurs during power-down mode if reset occurs during normal operation program counter (pc) lower three bits of address 0000h are transferred to pc1 1- 8, and the contents of 0001h to pc7 - 0. lower three bits of address 0000h are transferred to pc1 1- 8, and the contents of 0001h to pc7 - 0. program status word (psw): carry flag (c) retained undefined skip flag (sc0 - sc2) 0 0 interrupt status flags (is0, is1) 0 0 bank enable flags (emb, erb) bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. stack pointer (sp) undefined undefined data memory (ram): general registers e, a, l, h, x, w, z, y values retained undefined general-purpose registers values retained (note) undefined bank selection registers (smb, srb) 0, 0 0, 0 bsc register (bsc0 - bsc3) 0 0 clocks: power control register (pcon) 0 0 clock output mode register (clmod) 0 0 interrupts: interrupt request flags ( irqx) 0 0 interrupt enable flags ( iex) 0 0 interrupt priority flag (ipr) 0 0 interrupt master enable flag (ime) 0 0 int0 mode register (imod0) 0 0 int1 mode register (imod1) 0 0 intk mode register (imodk) 0 0 note: the values of the 0f8h-0fdh are not retained when a reset signal is input
ks57c 0502/c0504/p0504 microcontroller reset 9? 3 table 9?1. hardware register values after reset (continued) hardware component or subcomponent if reset occurs during power-down mode if reset occurs during normal operation i/o ports: output buffers off off output latches 0 0 port mode flags (pm) 0 0 pull-up resistor mode reg (pumod) 0 0 port 2 mode register (pwmod) 0 0 port open-drain enable register (pne) 0 0 watch-dog timer: wdt mode register (wdmod) a5h a5h wdt clear flag (wdtcf) 0 0 basic timer: count register (bcnt) undefined undefined mode register (bmod) 0 0 timer/counter 0: count registers (tcnt0) 0 0 reference registers (tref0) ffh, ffffh ffh, ffffh mode registers (tmod0) 0 0 output enable flags (toe0) 0 0 watch timer: watch timer mode register (wmod) 0 0 comparator comparator mode register (cmod) 0 0 comparison result register undefined undefined serial i/o interface: sio mode register (smod) 0 0 sio interface buffer (sbuf) values retained undefined
reset ks57c 0502/c0504/p0504 microcontroller 9? 4 notes
ks57c 0502/c0504/p0504 microcontroller i/o ports 10? 1 10 i/o ports overview the KS57C0502/c0504 has two input ports and five i/o ports. pin addresses for all i/o ports are mapped to locations ff0h?ff6h in bank 15 of the ram. the contents of i/o port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. there are total of 6 input pins and 18 configurable i/o pin, including 8 high current i/o pins for a maximum number of 24 i/o pins. port mode flags port mode flags (pm) are used to configure i/o ports 0 and 3 (port mode group 1), port 4 (port mode group 2), and ports 5 and 6 (port mode group 3) to input or output mode by setting or clearing the corresponding i/o buffer. pm flags are stored in three 8-bit registers in ram area fe8h?fedh, and are addressable by 8-bit write instructions only. port 2 mode register port 2 (p2.0?p2.3) can be used as either for analog input or for digital input. p2mod register settings determines port 2 mode (analog or digital input) for specific port 2 pins. pull-up resistors pull-up resistors are assignable to input pins of ports 0, 1, 3, 4, 5 and 6. when a configurable i/o port pin serves as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up resis tor is enabled by a corresponding bit setting in the pull-up resistor mode register (pumod). pumod control register the pull-up mode register (pumod) is an 8-bit register used to assign internal pull-up resistors by software to specific i/o ports. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding pumod bit setting. pumod is mapped to ram address fdch?fddh and is addressable by 8-bit write instructions only. reset clears pumod register values to logic zero, automatically disconnecting all software- assignable port pull-up resis tors.
i/o ports ks57c 0502/c0504/p0504 microcontroller 10? 2 table 10?1. i/o port overview port i/o pins pin names address function description 0 i/o 3 p0.0?p0.2 ff0h 3-bit i/o port. 1-bit and 3-bit read/write and test is possible. individual pins are software configurable as in - put or output. 3-bit pull-up resistors are assignable by software. 1 i 2 p1.0?p1.1 ff1h 2-bit input port. 1-bit and 2-bit read and test is possible. 2-bit pull-up resistors are software assignable. 2 i 4 p2.0?p2.3 ff2h 4-bit analog or digital input port. 1-bit or 4-bit read and test possible. 3 i/o 3 p3.0?p3.2 ff3h same as port 0. 4, 5 i/o 8 p4.0?p4.3 p5.0?p5.3 ff4h ff5h 4-bit i/o ports. 1 -, 4-, and 8-bit read/write/test is possible. pins are individually configurable as input or output. ports 4 and 5 can be paired to sup port 8-bit data transfer. 4-bit pull-up registers are software assignable to input pins and are automatically disabled for output pins. the n-channel open drain or push-pull output can be selected by software (1-bit unit) 6 i/o 4 p6.0?p6.3 ff6h 4-bit i/o ports. pins are individually soft ware configurable as input or output. 1-bit and 4 -bit read/write/test is possible. 4-bit pull -up resistors are software assignable. table 10?2. i/o port pin status during instruction execution instruction type example input mode status output mode status 1-bit test 1-bit input 4-bit input 8-bit input btst ldb ld ld p0.1 c,p1.3 a,p6 ea,p4 input or test data at each pin input or test data at output latch 1-bit output bitr p3.0 output latch contents undefined output pin status is modified 4-bit output 8-bit output ld ld p2,a p6,ea transfer accumulator data to the output latch transfer accumulator data to the output pin
ks57c 0502/c0504/p0504 microcontroller i/o ports 10? 3 port mode flags (pm flags) port mode flags (pm) are used to configure i/o ports 0 and 3?6 to input or output mode by setting or clearing the corresponding i/o buffer. pm flags are stored in three 8-bit registers in ram area fe8h?fedh, and are ad - dressable by 8-bit write instructions only. for convenient program reference, pm flags are organized into three groups ? pmg1, pmg2, and pmg3, as shown in table 10?3. table 10?3. port mode groups and corresponding i/o ports port mode group id corresponding i/o ports port mode group address pmg1 ports 0 and 3 fe8h?fe9h pmg2 port 4 feah?febh pmg3 ports 5 and 6 fech?fedh when a pm flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. reset clears all port mode flags to logic zero, automatically configuring the corresponding i/o ports to input mode. table 10?4. port mode flag map pm group id address bit 3 bit 2 bit 1 bit 0 pmg1 fe8h "0" pm0.2 pm0.1 pm0.0 fe9h "0" pm3.2 pm3.1 pm3.0 pmg2 feah pm4.3 pm4.2 pm4.1 pm4.0 febh "0" "0" "0" "0" pmg3 fech pm5.3 pm5.2 pm5.1 pm5.0 fedh pm6.3 pm6.2 pm6.1 pm6.0 note: if bit = "0", the corresponding i/o pin is set to input mode. if bit = "1", the pin is set to output mode. all flags are cleared to "0" following reset . + + programming tip ? configuring i/o ports as input or output configure p0.0 and p3.0 as an output port and the other ports as input ports: bits emb smb 15 ld ea,#11h ld pmg1,ea ; p0.0 and p3.0 ? output ld ea,#00h ld pmg2,ea ; p4 ? input ld ea,#00h ld pmg3,ea ; p5, p6 ? input
i/o ports ks57c 0502/c0504/p0504 microcontroller 10? 4 port 2 mode register (p2mod) p2mod register settings determine if port 2 is used either for analog input or for digital input. p2mod register is 4-bit write only register. p2mod is mapped to address fe2h and initialized to zero by a reset , configuring port 2 as an analog input port. fe2h p2mod.3 p2mod.2 p2mod.1 p2mod.0 when bit is set to "1", the corresponding pin is configured as a digital input pin. when set to "0", configured as an analog input pin: p2mod.0 for p2.0, p2mod.1 for p2.1, p2mod.2 for p2.2, and p2mod.3 for p2.3 . pull-up resistor mode register (pumod) the pull-up resistor mode register (pumod) is an 8-bit register used to assign internal pull-up resistors by soft ware to specific i/o ports. when a configurable i /o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding pumod bit setting. pumod is mapped to ram address fdch?fddh and is addressable by 8-bit write instructions only. reset clears pumod register values to logic zero, automatically disconnecting all software- assignable port pull-up resis tors. table 10?5. pull-up resistor mode register (pumod) organization address bit 3 bit 2 bit 1 bit 0 fdch pumod.3 "0" pumod.1 pumod.0 fddh "0" pumod.6 pumod.5 pumod.4 note: when bit = "1", a pull-up resistor is assigned to the corresponding i/o port: pumod.3 for port 3, pumod.6 for port 6, and so on. n-channel open-drain enable register (pne ) address bit 3 bit 2 bit 1 bit 0 pne fdah pne4.3 pne4.2 pne4.1 pne4.0 fdbh pne5.3 pne5.2 pne5.1 pne5.0 the n-channel, open-drain mode register, pne, is used to configure ports 4 and 5 to n-channel, open-drain mode or as push-pull outputs. when a bit in the pne register is set to "1", the corresponding output pin is configured to n-channel, open- drain; when set to " 0 ", the output pin is configured to push-pull; pne4.3 for p4.3, pne4.2 for p4.2, pne4.1 for p4.1, pne4.0 for p4.0, pne5.3 for p5.3, pne5.2 for p5.2, pne5.1 for p5.1 and pne5.0 for p5.0. + + programming tip ? enabling and disabling i/o port pull-up resistors p6 enable pull-up resistors, p0, p1, p3, p4 and p 5 disable pull-up resistors. bits emb smb 15 ld ea,#40h ld pumod,ea ; p6 enable
ks57c 0502/c0504/p0504 microcontroller i/o ports 10? 5 port 0 circuit diagram sck sck so si p0.2 latch p0.1 latch p0.0 latch pm0.2 pm0.1 pm0.0 v dd when a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). note: p0.0 / sck smod.7 smod.6 smod.5 smod.1 pumod.0 pumod.0 pumod.0 p0.1 / so p0.2 / si figure 10?1. i/o port 0 circuit diagram
i/o ports ks57c 0502/c0504/p0504 microcontroller 10? 6 port 1 circuit diagram int0 int1 p1.0 / int0 pumod.1 p1.1 / int1 v dd v dd n/r circuit n/r = noise reduction imod0 figure 10?2. input port 1 circuit diagram
ks57c 0502/c0504/p0504 microcontroller i/o ports 10? 7 port 2 circuit diagram p2.0 / cin0 p2.1 / cin1 p2.2 / cin2 p2.3 / cin3 analog input digital input analog input analog input analog input digital input digital input digital input external reference figure 10?3. port 2 circuit diagram
i/o ports ks57c 0502/c0504/p0504 microcontroller 10? 8 port 3 circuit diagram pm3.2 pm3.1 pm3.0 v dd pumod.3 pumod.3 pumod.3 when a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). note: 1, 4 tcl0 tc0 clock output clock output p3.0 / tcl0 p3.1 / tclo0 p3.2 / clo output latch 1, 4 m u x figure 10?4. port 3 circuit diagram
ks57c 0502/c0504/p0504 microcontroller i/o ports 10? 9 ports 4 and 5 circuit diagram px.b v dd 1, 4, 8 8 p-ch n-c h v ss m u x p-ch pumod.b b=4, 5 output latch pne pmx.b x=4, 5 b=0, 1, 2, 3 8 8 figure 10?5. circuit diagram for ports 4 and 5
i/o ports ks57c 0502/c0504/p0504 microcontroller 10? 10 port 6 circuit diagram p6.0 / ks0 p6.1 / ks1 p6.2 / ks2 p6.3 / buz v dd when a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). note: 1, 4 1, 4 output latch pm6.2 pm6.3 pm6.1 pumod.6 pumod.6 pumod.6 pumod.6 pm6.0 m u x figure 10?6. port 6 circuit diagram
KS57C0502/c0504/p0504 microcontroller timers and timer/counter 11? 1 11 timers and timer/counter overview there are three timer and timer/counter function modules: ? 8-bit basic timer (bt) ? 8-bit timer/counter 0 (tc0) ? watch timer (wt) the 8-bit basic timer (bt) is the microcontroller's main interval timer. it generates a interrupt request at a fixed time interval by making the appropriate modification to the mode register. the basic timer also functions as a 'watchdog' timer and is used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a reset . the 8-bit timer/counter 0 (tc0) is programmable timer/counter that is used primarily for event counting and for clock frequency modification and output. in addition, tc0 generates a clock signal that can be used by the serial i/o interface. the watch timer (wt) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. watch timer functions include real-time and watch-time measurement, system clock in terval timing, and generation of buzzer output.
timers and timer/counter KS57C0502/c0504/p05 04 microcontroller 11? 2 basic timer (bt) overview the 8-bit basic timer (bt) has four functional components: ? clock selector logic ? 4-bit mode reg ister (bmod) ? 8-bit counter register (bcnt) the basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. you can use the basic timer as a "watchdog" timer for monitoring system events or use bt output to stabilize clock oscillation when stop mode is released by an interrupt and following reset . use the basic timer mode register, bmod, to turn the bt on and off, to select input clock frequency, and to con trol interrupt or stabilization intervals. interval timer function the measurement of elapsed time intervals is the basic timer's primary function. the standard interval is 256 bt clock pulses. to restart the basic timer, set bit 3 of the mode register bmod to logic one. the input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to bmod.2?bmod.0. the 8-bit counter register, bcnt, is incremented each time a clock signal is detected that corresponds to the frequency selected by bmod. bcnt continues incrementing as it counts bt clocks until an overflow occurs. an overflow causes the bt interrupt request flag (irqb) to be set to logic one to signal that the designated time interval has elapsed. an interrupt request is then generated, bcnt is cleared to logic zero, and counting continues from 00h. watchdog timer function the basic timer can also be used as a "watch - dog" timer to detects inadvertent program loop, that is, system or program operation error. for this purpose, instruction that clear the watch-dog timer( bits wdtcf ) should be executed at proper points in a program within a given period. if an instruction that clears the watch-dog timer is not executed within the period and the watch-dog timer overflows, reset signal is generated and system is restarted with reset status. an operation of watch-dog timer is as follows: ? write some value(except #5ah) to watch-dog timer mode register, wdmod. ? if wdcnt overflows, system reset is generated. oscillation stabilization interval control bits 2?0 of the bmod register are used to select the input clock frequency for the basic timer. this setting also determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when power-down mode is released by an interrupt. when a reset signal is generated , the standard stabilization interval for system clock oscillation following a reset is 31.3 ms at 4.19 mhz.
KS57C0502/c0504/p0504 microcontroller timers and timer/counter 11? 3 table 11?1. basic timer register overview register name type description size ram address addressing mode reset value bmod control controls the clock frequency (mode) of the basic timer; also, the oscillation stabilization interval after power-down mode release or reset 4-bit f85h 4-bit write- only; bmod.3: also 1-bit writeable "0" bcnt counter counts clock pulses matching the bmod frequency setting 8-bit f86h - f87h 8-bit read-only u * wdmod control controls watch-dog timer operation. 8-bit f 9 8h ? f 99 h 8-bit write - only a5h wdtcf control clear the watch-dog time r's counter. 1 -bit f9ah.3 1 -bit write - only "0" * 'u' means the value is undetermined after a reset . "clear" signal bits instruction clock selector bcnt irqb interrupt request overflow cpu clock start signal (power-down release) 1-bit r/w clock input clear irqb 4 clear bcnt 8 bmod.3 bmod.2 bmod.1 bmod.0 wdmod wdtcnt reset generation 8 wdtcf delay wait* reset stop bits instruction *wait means -stabilization time after reset - stabilization time after stop mode release 1 pulse period=bt input clock 2 8 (1/2 duty) reset overflow clear 3-bit counter figure 11?1. basic timer circuit diagram
timers and timer/counter KS57C0502/c0504/p05 04 microcontroller 11? 4 basic timer mode register (bmod) the basic timer mode register, bmod, is a 4-bit write-only register located at ram address f85h. bit 3, the basic timer start control bit, is also 1-bit addressable. all bmod values are set to logic zero following reset and interrupt request signal generation is set to the longest interval. (bt counter operation cannot be stopped.) bmod settings have the following effects: ? restart the basic timer, ? control the frequency of clock signal input to the basic timer, and ? determine time interval required for clock oscillation to stabilize following the release of stop modes by an interrupt. by loading different values into the bmod register, you can dynamically modify the basic timer clock frequency during program execution. four bt frequencies, ranging from fx/2 12 (1.02 khz) to fx/2 5 (131 khz), are se lectable . since bmod's reset value is logic zero, the default clock frequency setting is fx/2 12 . (khz frequencies assume a system clock ( fx) frequency of 4.19 mhz.) the most significant bit of the bmod register, bmod.3, is used to start the basic timer again. when bmod.3 is set to logic one (enabled) by a 1-bit write instruction, the contents of the bt counter register (bcnt) and the bt interrupt request flag (irqb) are both cleared to logic zero, and timer operation is restarted. the combination of bit settings in the remaining three registers ? bmod.2, bmod.1, and bmod.0 ? determine the clock input frequency and oscillation stabilization interval. table 11?2. basic timer mode register (bmod) organization bmod.3 basic timer enable/disable control bit 1 start basic timer; clear irqb, bcnt, and bmod.3 to "0" bmod.2 bmod.1 bmod.0 basic timer input clock oscillation stabilization 0 0 0 fx/2 12 (1.02 khz) 2 20 / fx (250 ms) 0 1 1 fx/2 9 (8.18 khz) 2 17 / fx (31.3 ms) 1 0 1 fx/2 7 (32.7 khz) 2 15 / fx (7.82 ms) 1 1 1 fx/2 5 (131 khz) 2 13 / fx (1.95 ms) notes : 1. clock frequencies and stabilization intervals assume a system oscillator clock frequency ( fx) of 4.19 mhz. 2. fx = system clock frequency. 3. oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released. 4. the standard stabilization time for system clock oscillation following a reset is 31.3 ms at 4.19 mhz.
KS57C0502/c0504/p0504 microcontroller timers and timer/counter 11? 5 basic timer counter (bcnt) bcnt is an 8-bit counter register for the basic timer. it is mapped to ram addresses f86h?f87h and can be addressed by 8-bit read instructions. reset leaves the bcnt register value undetermined. bcnt is automatically cleared to logic zero whenever the bmod register control bit (bmod.3) is set to "1" to restart the basic timer. it is incremented each time a clock pulse of the frequency determined by the current bmod bit settings is detected. when bcnt has incremented to hexadecimal 'ffh' (256 clock pulses), it is cleared to '00h' and an overflow is generated. the overflow causes the interrupt request flag, irqb, to be set to logic one. when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. note always execute a bcnt read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. if, after two consecutive reads, the bcnt values match, you can select the latter value as valid data. until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met. basic timer operation sequence the basic timer's sequence of operations may be summarized as follows: 1. set bit bmod.3 to logic one to restart basic timer operation 2. bcnt is incremented by one after each clock pulse correspond ing to bmod selection 3. bcnt overflows if bcnt 3 255 (ffh) 4. when an overflow occurs, the irqb flag is set to logic one by hardware 5. the interrupt request is generated 6. bcnt is automatically cleared to logic zero (bcnt = 00h) 7. bcnt resumes counting bt clock pulse
timers and timer/counter KS57C0502/c0504/p05 04 microcontroller 11? 6 + + programming tip ? using the basic timer 1. to read the basic timer count register (bcnt): bits emb smb 15 bcntr ld ea,bcnt ld yz,ea ld ea,bcnt cpse ea,yz jr bcntr 2. whe n stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms: bits emb smb 15 ld a,#0bh ld bmod,a ; wait time is 31.3 ms stop ; set stop power-down mode nop nop nop normal operating mode stop mode idle mode (31.3 ms) cpu operation stop instruction stop mode is released by interrupt normal operating mode 3. to set the basic timer interrupt interval time to 1.95 ms (at 4.19 mhz): bits emb smb 15 ld a,#0fh ld bmod,a ei bits ieb ; basic timer interrupt enable flag is set to "1" 4. clear bcnt and the irqb flag and restart the basic timer: bits emb smb 15 bits bmod.3
KS57C0502/c0504/p0504 microcontroller timers and timer/counter 11? 7 watch-dog timer mode register ( wd mod) the watch-dog timer mode register, wd mod, is a 8 -bit write-only register located at ram address f 98 h - f 99 h. wdmod register controls to enable or disable the watch-dog timer function. wd mod values are set to logic "a5h" following reset and this value enable the watch-dog timer, and watch-dog time r's period is set to the longest interval because bt overflow signal is generat ed with the longest interval. (bt counter operation cannot be stopped.) wdmod - watch ? dog timer mode control register f 99 h ,f98h bit 3 2 1 0 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 1 0 1 0 0 1 0 1 read/write w w w w w w w w wd mod watch-dog timer enable/disable control 5ah disable watch-dog timer function any other value enable watch-dog timer function watch-dog timer counter ( wd cnt) wd cnt is an 3 -bit counter . wd cnt is automatically cleared to logic zero whenever the wdtcf register control bit ( wdtcf ) is set to "1" to restart the wdcnt . reset, stop, and wait signal clear the wdcnt to logic zero also. wdcnt is incremented each time a clock pulse of the overflow frequency determined by the current bmod bit settings. when wd cnt has incremented to hexadecimal ' 07 h' ( 8 bt overflow pulses), it is cleared to '00h' and an overflow is generated. the overflow causes the system reset . when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. watch-dog time r's counter clear flag ( wdt c f ) wdtcf(f9ah.3) setting clear the wdt 's counter to zero and restart the wdt 's counter. table 11-3. w a tch-dog timer interval time bmod b t input clock wdcnt input clock wdt interval time main clock x000b 2 12 / fx 2 12 / fx 2 8 2 12 / fx 2 8 2 3 2 sec x011b 2 9 / fx 2 9 / fx 2 8 2 9 / fx 2 8 2 3 250 msec x101b 2 7 / fx 2 7 / fx 2 8 2 7 / fx 2 8 2 3 62.5 msec x111b 2 5 / fx 2 5 / fx 2 8 2 5 / fx 2 8 2 3 15.6 msec notes : 1. clock frequencies assume a system oscillator clock frequency ( fx) of : main clock 4.19mhz 2. fx = system clock frequency.
timers and timer/counter KS57C0502/c0504/p05 04 microcontroller 11? 8 8-bit timer/counter 0 (tc0) timer/counter 0 (tc0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. to indicate that an event has occurred, or that a specified time interval has elapsed, tc0 generates an interrupt request. by counting signal transitions and comparing the current counter value with the reference register value, tc0 can be used to measure specific time intervals. tc0 has a reloadable counter that consists of two parts: an 8-bit reference register (tref0) into which you write the counter reference value, and an 8-bit counter register (tcnt0) whose value is automatically incremented by counter logic. an 8-bit mode register, tmod0, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. you can modify the basic frequency dynamically by loading new values into tmod0 during program execution. tc0 function summary 8-bit programmable timer generates interrupts at specific time intervals based on the selected clock fre - quency. external event counter counts various system "events" based on edge detection of external clock sig - nals at the tc0 input pin, tcl0. to start the event counting operation, tmod0.2 is set to "1" and tmod0.6 is cleared to "0". arbitrary frequency output outputs selectable clock frequencies to the tc0 output pin, tclo0. external signal divider divides the frequency of an incoming external clock signal according to a modi fiable reference value (tref0), and outputs the modified frequency to the tclo0 pin. serial i/o clock source outputs a modifiable clock signal for use as the sck clock source.
KS57C0502/c0504/p0504 microcontroller timers and timer/counter 11? 9 tc0 component summary mode register (tmod0) activates the timer/counter and selects the internal clock frequency or the external clock source at the tcl0 pin. reference register (tref0) stores the reference value for the desired number of clock pulses between in - terrupt requests. counter register (tcnt0) counts internal or external clock pulses based on the bit settings in tmod0 and tref0. clock selector circuit together with the mode register (tmod0), lets you select one of four internal clock frequencies, or external clock frequency. 8-bit comparator determines when to generate an interrupt by comparing the current value of the counter register (tcnt0) with the reference value previously programmed into the reference register (tref0). output latch (tol0) where a tc0 interrupt request or clock pulse is stored pending output to the serial i/o circuit or to the tc0 output pin, tclo0. when the contents of the tcnt0 and tref0 registers coincide, the timer/counter interrupt request flag (irqt0) is set to "1", the status of tol0 is in verted, and an interrupt is generated. output enable flag (toe0) you must set this flag to logic one before the contents of the tol0 latch can be output to tclo0. interrupt request flag (irqt0) this flag is cleared when tc0 operation starts and the tc0 interrupt service routine is executed and is enabled whenever the counter value and reference value coincide. interrupt enable flag (iet0) must be set to logic one before the interrupt requests generated by timer/counter can be processed. table 11? 4 . tc0 register overview register name type description size ram address addressing mode reset value tmod0 control controls tc0 restart (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6?4) 8-bit f90h?f91h 8-bit write- only; (tmod0.3 is also 1 -bit write-only) "0" tcnt0 counter counts clock pulses matching the tmod0 frequency setting 8-bit f94h?f95h 8-bit read-only "0" tref0 reference stores reference value for the timer/counter 0 interval setting 8-bit f96h?f97h 8-bit write-only ffh toe0 flag controls timer/counter 0 output to the tclo0 pin 1-bit f92h.2 1-bit write-only "0"
timers and timer/counter KS57C0502/c0504/p05 04 microcontroller 11? 10 tcl0 tclo0 serial i/o tcnt0 clear inverted clear set clear clocks (fx/2 , fx/2 , fx/2 , fx) 10 6 4 8 8 clock selector 8-bit comparator p3.0 tol0 p3.1 latch toe0 irqt0 pm3.1 tmod0.7 tmod0.6 tmod0.5 tmod0.4 tmod0.3 tmod0.2 tmod0.1 tmod0.0 tref0 8 figure 11?2. tc0 circuit diagram tc0 enable/disable procedure enable timer/counter 0 ? set tmod.2 to logic one (ram address f90h.2) ? set the tc0 interrupt enable flag iet0 to logic one (ram address fbch.1) ? set tmod0.3 to logic one (ram address f90h.3) tcnt0, irqt0, and tol0 are cleared to logic zero, and timer/counter operation starts. disable timer/counter ? set tmod0.2 to logic zero (ram address f90h.2) clock signal input to the counter register tcnt0 is halted. the current tcnt0 value is retained and can be read if necessary.
KS57C0502/c0504/p0504 microcontroller timers and timer/counter 11? 11 tc0 programmable timer/counter function timer/counter 0 can be programmed to generate interrupt requests at various intervals, based on the system clock frequency you select. the 8-bit tc0 mode register, tmod0, is used to activate the timer/counter and to select the clock frequency. the reference register, tref0, stores your value for the number of clock pulses to be generated between inter - rupt requests. the counter register, tcnt0, counts the incoming clock pulses, which are compared to the tref0 value as tcnt0 is incremented. when there is a match (tref0 = tcnt0), an interrupt request is generated. to program timer/counter to generate interrupt requests at specific intervals, you choose one of four internal clock frequencies (divisions of the system clock, fx) and load your own counter reference value into the tref0 register. tcnt0 is incremented each time an internal counter pulse is detected with the reference clock frequency specified by tmod0.4?tmod0.6 settings. to generate an interrupt request, the tc0 interrupt request flag (irqt0) is set to logic one, the status of tol0 is inverted, and the interrupt is generated. the content of tcnt0 is then cleared to 00h, and tc0 continues counting. the interrupt request mechanism for the programmable timer/counter consists of the tc0 interrupt enable flag iet0 and the tc0 interrupt request flag irqt0. tc0 operation sequence the general sequence of operations when using tc0 as a programmable timer/counter can be summarized as follows: 1. set tmod0.2 to "1" to enable tc0 2. set tmod0.6 to "1" to enable the system clock ( fx) input 3. set tmod0.5 and tmod0.4 bits to desired internal frequency (fx/2 n ) 4. load a value to tref0 to specify the interval between interrupt requests 5. set the tc0 interrupt enable flag (iet0) to "1" 6. set tmod0.3 bit to "1" to clear tcnt0, irqt0, and tol0, and start counting 7. tcnt0 increments with each internal clock pulse 8. when the comparator shows tcnt0 = tref0, the irqt0 flag is set to "1" 9. output latch (tol0) logic toggles high or low 10. interrupt request is generated 11. tcnt0 is cleared to 00h and counting resumes 12. programmable timer/counter operation continues until tmod0.2 is cleared to "0".
timers and timer/counter KS57C0502/c0504/p05 04 microcontroller 11? 12 tc0 event counter function timer/counter 0 can be used to monitor or detect system 'events' by using the external clock input at the tcl0 pin (i/o port 3.0) as the counter source. the tc0 mode register is used to specify rising or falling edge detection for incoming clock signals. the counter register tcnt0 is incremented each time the selected state transition of the external clock signal occurs. to activate the tc0 event counter function, ? set tmod0.2 to "1" to enabl e tc0 ? clear tmod0.6 to "0" to select the external clock source at the tcl0 pin ? select tcl0 edge detection for rising or falling signal edges by loading the appropriate values to tmod0.5 and tmod0.4. ? p3.0 must be set to input mode. table 11? 5 . tmod0 settings for tcl0 edge detection tmod0.5 tmod0.4 tcl0 edge detection 0 0 rising edges 0 1 falling edges with the exception of the different tmod0.4?tmod0.6 settings, the operation sequence for tc's event counter function is identical to its programmable counter/timer function.
KS57C0502/c0504/p0504 microcontroller timers and timer/counter 11? 13 tc0 clock frequency output using timer/counter, you can output a modifiable clock frequency to the tc0 clock output pin, tclo0. to select the clock frequency, you load appropriate values to the tc0 mode register, tmod0. the clock interval is determined by loading the desired reference value into the reference register tref0. then, to enable the output to the tclo0 pin at i/o port 3.1, the following conditions must be met: ? tc0 output enable flag toe0 must be set to "1" ? i/o mode flag for p3.1 (pm3.1) must be set to output mode ("1") ? output latch value for p3.1 must be set to "0" in summary, the operational sequence required to output a tc0-generated clock signal to the tclo0 pin is as follows: 1. load your reference value to tref0 2. set the clock frequency in tmod0 3. initiate tc0 clock output to tclo0 (tmod0.2 = "1") 4. set port 3 mode flag (pm3.1) to "1" 5. set p3.1 ou tput latch to "0" 6. set toe0 flag to "1" each time tcnt0 overflows and an interrupt request is generated, the state of the output latch tol0 is in - verted and the tc0-generated clock signal is output to the tclo0 pin. + + programming tips ? tc0 signal output to the tclo0 pin output a 30 ms pulse width signal to the tclo0 pin: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea ld ea,#20h ld pmg1,ea ; p3.1 ? output mode bitr p3.1 ; p3.1 clear bits toe0
timers and timer/counter KS57C0502/c0504/p05 04 microcontroller 11? 14 tc0 serial i/o clock generation timer/counter 0 can supply a clock signal to the clock selector circuit of the serial i/o interface for data shifter and clock counter operations. (these internal sio operations are controlled in turn by the sio mode register, smod). this clock generation function enables you to adjust data transmission rates across the serial interface. use tmod0 and tref0 register settings to select the frequency and interval of the tc0 clock signals to be used as sck input to the serial interface. the generated clock signal is then sent directly to the serial i/o clock selector circuit ? not through the port 3.1 latch and tclo0 pin. tc0 external input signal divider by selecting an external clock source and loading a reference value into the tc0 reference register, tref0, you can divide the incoming clock signal by the tref0 value and then output this modified clock frequency to the tclo0 pin. the sequence of operations used to divide external clock input may be summarized as follows: 1. load a signal divider value to the tref0 buffer register 2. clear tmod0.6 to "0" to enable external clock input at the tcl0 pin 3. set tmod0.5 and tmod0.4 to desired tcl0 signal edge detection 4. set port 3.1 mode flag (pm3.1) to output ("1") 5. set p3.1 output latch to "0" 6. set toe0 flag to "1" to enable output of the divided frequency divided clock signals are then output to the tclo0 pin. + + programming tip ? external tcl0 clock output to the tclo0 pin output external tcl0 clock pulse to the tclo0 pin (divide by four): external (tcl0) clock pulse tclo0 output pulse bits emb smb 15 ld ea,#01h ld tref0,ea ld ea,#0ch ld tmod0,ea ld ea,#20h ld pmg1,ea ; p3.1 ? output mode bitr p3.1 ; p3.1 clear bits toe0
KS57C0502/c0504/p0504 microcontroller timers and timer/counter 11? 15 tc0 mode register (tmod0) tmod0 is the 8-bit mode control register for timer/counter. it is located at ram addresses f90h?f91h and is addressable by 8-bit write instructions. one bit, tmod0.3, is also 1-bit writeable. reset clears all tmod0 bits to logic zero and disables tc0 operations. f90h tmod0.3 tmod0.2 "0" "0" f91h "0" tmod0.6 tmod0.5 tmod0.4 tmod0.2 is the enable/disable bit for timer/counter. when tmod0.3 is set to "1", the contents of tcnt0, irqt0, and tol0 are cleared, counting starts from 00h, and tmod0.3 is automatically reset to "0" for normal tc0 operation. when tc0 operation stops (tmod0.2 = "0"), the contents of the tc0 counter register, tcnt0, are re tained until tc0 is re-enabled. use tmod0.6, tmod0.5, and tmod0.4 bit settings together to select the tc0 clock source. this selec tion involves two variables: ? synchronization of timer/counter operations with either the rising edge or the falling edge of the clock sig - nal input at the tcl0 pin, and ? selection of one of four frequencies, based on division of the incoming system clock freq uency, for use in internal tc0 operation. table 11? 6 . tc0 mode register (tmod0) organization bit name setting resulting tc0 function address tmod0.7 0 msb value always logic zero tmod0.6 f91h tmod0.5 0,1 specify input clock edge and internal frequency tmod0.4 tmod0.3 1 clear tcnt0, irqt0, and tol0 and resume counting immedi ately (this bit is automatically cleared to logic zero immediately after counting resumes.) tmod0.2 0 disable timer/counter; retain tcnt0 contents f90h 1 enable timer/counter tmod0.1 0 value always logic zero tmod0.0 0 lsb value always logic zero
timers and timer/counter KS57C0502/c0504/p05 04 microcontroller 11? 16 table 11? 7 . tmod0.6, tmo0.5, and tmod0.4 bit settings tmod0.6 tmod0.5 tmod0.4 resulting counter source and clock frequency 0 0 0 external clock input (tcl0) on rising edges 0 0 1 external clock input (tcl0) on falling edges 1 0 0 fx/2 10 = 4.09 khz 1 0 1 fx /2 6 = 65.5 khz 1 1 0 fx/2 4 = 262 khz 1 1 1 fx = 4.19 mhz note : ' fx' = system clock + + programming tip ? restarting tc0 counting operation 1. set tc0 timer interval to 4.09 khz: bits emb smb 15 ld ea,#4ch ld tmod0,ea ei bits iet0 2. clear tcnt0, irqt0, and tol0 and restart tc0 counting operation: bits emb smb 15 bits tmod0.3
KS57C0502/c0504/p0504 microcontroller timers and timer/counter 11? 17 tc0 counter register (tcnt0) the 8-bit counter register for timer/counter, tcnt0, is mapped to ram addresses f94h?f95h. it is read-only and can be addressed by 8-bit ram control instructions. reset sets all tcnt0 register values to logic zero (00h). whenever tmod0.3 are enabled, tcnt0 is cleared to logic zero and counting begins. the tcnt0 register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the tmod0 register (specifically, tmod0.6, tmod0.5, and tmod0.4). each time tcnt0 is incremented, the new value is compared to the reference value stored in the tc0 refer - ence register, tref0. when tcnt0 = tref0, an overflow occurs in the tcnt0 register, the interrupt request flag, irqt0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter inter val has elapsed. counting starts count clock tcnt0 tol0 tref0 reference value = n 0 1 2 . . . n-1 n 0 1 2 . . . n-1 0 1 2 n n . . . irqt0 set irqt0 set interval time figure 11?3. tc0 timing diagram
timers and timer/counter KS57C0502/c0504/p05 04 microcontroller 11? 18 tc0 reference register (tref0) the tc0 reference register tref0 is an 8-bit write-only register that is mapped to ram locations f96h and f97h. it is addressable by 8-bit ram control instructions. reset initializes the tref0 value to 'ffh'. tref0 is used to store a reference value to be compared to the incrementing tcnt0 register in order to iden - tify an elapsed time interval. reference values will differ depending upon the specific function that tc0 is being used to perform ? as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. during timer/counter operation, the value loaded into the reference register compared to the tcnt0 value. when tcnt0 = tref0, the tc0 output latch (tol0) is inverted and an interrupt request is generated to signal the interval or event. the tref0 value, together with the tmod0 clock frequency selection, determines the specific tc0 timer in - terval. use the following formula to calculate the correct value to load to the tref0 reference register: tc0 timer interval = (tref0 value + 1) 1 tmod0 frequency setting ( assuming a tref0 value 1 0 ) tc0 output enable flag (toe0) the 1-bit timer/counter 0 output enable flag toe0 controls output from timer/counter 0 to the tclo0 pin. toe0 is mapped to ram location f92h.2 and is addressable by 1-bit read and write instructions. bit 3 bit 2 bit 1 bit 0 f92h 0 toe0 0 0 when you set the toe0 flag to "1", the contents of tol0 can be output to the tclo0 pin. whenever a reset occurs, toe0 is automatically set to logic zero, disabling all tc0 output. even when the toe0 flag is disabled, timer/counter can continue to output an internally-generated clock frequency, via tol0, to the serial i/o clock selector circuit. tc0 output latch (tol0) tol0 is the output latch for timer/counter. when the 8-bit comparator detects a correspondence between the value of the counter register tcnt0 and the reference value stored in the tref0 buffer, the tol0 value is inverted ? the latch toggles high-to-low or low-to-high. whenever the state of tol0 is switched, the tc0 signal is output. tc0 output may be directed to the tclo0 pin at p3.1, or it can be output directly to the serial i/o clock selector circuit as the sck signal. assuming tc0 is enabled, when bit 3 of the tmod0 register is set to "1", the tol0 latch is cleared to logic zero, along with the counter register tcnt0 and the interrupt request flag, irqt0, and counting resumes immedi ately. when tc0 is disabled (tm od0.2 = "0"), the contents of the tol0 latch are retained and can be read, if necessary.
KS57C0502/c0504/p0504 microcontroller timers and timer/counter 11? 19 + + programming tip ? setting a tc0 timer interval to set a 30 ms timer interval for tc0, given fx = 4.19 mhz, follow these steps. 1. select the timer/counter mode register with a maximum setup time of 62.5 ms (assume the tc0 counter clock = fx/2 10 , and tref0 is set to ffh): 2. calculate the tref0 value: 30 ms = tref0 value + 1 4.09 khz tref0 + 1 = 30 ms 244 s = 122.9 = 7ah tref0 value = 7ah ? 1 = 79h 3. load the value 79h to the tref0 register: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea
timers and timer/counter KS57C0502/c0504/p05 04 microcontroller 11? 20 watch timer overview the watch timer is a multi-purpose timer consisting of three basic components: ? 8-bit watch timer mode register (wmod) ? clock selector ? frequency divider circuit watch timer functions include real-time and watch-time measurement and interval timing for the system clock. it is also used as a clock source for generating buzzer output. real-time and watch-time measurement to start watch timer operation, set bit 2 of the watch timer mode register, wmod.2, to logic one. the watch timer starts, the interrupt request flag irqw is automatically set to logic one, and interrupt requests commence in 0.5-second intervals. since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the irqw flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed. using a system clock source the watch timer can generate interrupts based on the system clock frequency. the system clock ( fx) is used as the signal source, according to the following for mula: watch timer clock ( fw) = system clock (fx) 128 = 32.768 khz (assuming fx = 4.19 mhz) buzzer output frequency generator the watch timer can generate a steady 2 khz, 4 khz, 8 khz, or 16 khz signal to the buz pin. to select the buz frequency you want, load the appropriate value to the wmod register. this output can then be used to actuate an external buzzer sound. to generate a buz signal, three conditions must be met: ? the wmod.7 register bit at f89h.3 is set to "1" ? the output latch for i/o port 6.3 is cleared to "0" ? the port 6.3 output mode flag (pm6.3) set to 'output' mode timing tests in high-speed mode by setting wmod.1 (f88h.1) to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. at its normal speed (wmod.1 = '0'), the watch timer generates an interrupt request every 0.5 sec onds. high-speed mode is useful for timing events for program debugging sequences.
KS57C0502/c0504/p0504 microcontroller timers and timer/counter 11? 21 watch timer circuit fx = system clock fw = watch timer frequency 8 irqw gnd fx/128 fw 32.768 khz fw/16 (2 khz) buz fw/8 (4 khz) fw/2 7 fw/2 (2 hz) 14 enable / disable fw/4 (8 khz) fw/2 (16 khz) wmod.7 0 wmod.5 wmod.4 0 wmod.2 wmod.1 0 selector circuit clock selector mux frequency dividing circuit p6.3 latch pm6.3 figure 11?4. watch timer circuit diagram
timers and timer/counter KS57C0502/c0504/p05 04 microcontroller 11? 22 watch timer mode register (wmod) the watch timer mode register wmod is used to select specific watch timer operations. it is mapped to ram lo cations f88h ?f89h and is 8-bit write-only addressable. reset sets all wmod bits to logic zero. f88h "0" wmod.2 wmod.1 "0" f89h wmod.7 "0" wmod.5 wmod.4 in brief, wmod settings control the following watch timer functions: ? watch timer speed control (wmod.1) ? enable/disable watch timer (wmod.2) ? buzzer frequency selection (wmod.4) (wmod.5) ? enable/disable buzzer output (wmod.7) table 11? 8 . watch timer mode register (wmod) organization bit name values function address wmod.7 0 disable buzzer (buz) signal output 1 enable buzzer (buz) signal output wmod.6 "0" always logic zero wmod.5 ? .4 0 0 2 khz buzzer (buz) signal output f89h 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output wmod.3 "0" always logic zero wmod.2 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer f88h wmod.1 0 normal mode; sets irqw to 0.5 seconds 1 high-speed mode; sets irqw to 3.91 ms wmod.0 0 always logic zero note : system clock frequency ( fx) is assumed to be 4.19 mhz.
KS57C0502/c0504/p0504 microcontroller timers and timer/counter 11? 23 + + programming tip ? using the watch timer 1. select a 0.5 second interrupt, and 2 khz buzzer enable: bits emb smb 15 ld ea,#80h ld pmg3,ea ; p6.3 ? output mode bitr p6.3 ; clear p6.3 output latch ld ea,#84h ld wmod,ea bits iew 2. sample rea l-time clock processing method: clock btstz irqw ; 0.5 second check ret ; no, return ? ; yes, 0.5 second interrupt generation ? ? ; increment hour, minute, second
timers and timer/counter KS57C0502/c0504/p05 04 microcontroller 11? 24 notes
ks57c 0502/c0504/p0504 microcontroller comparator 12? 1 12 comparator overview port 2 can be used as a analog input port for a comparator. the reference voltage for the 4-channel comparator can be supplied either internally or externally at p2.3. when internal reference voltage is used, four channels (p2.0?p2.3) are used for analog inputs and the internal reference voltage is varies at 16 levels. if an external reference voltage is input at p2.3, the other three pins (p2.0?p2.2) in port 2 are used for analog input. unused port 2 pins must be connected to v dd . when a conversion is completed, the result is saved in the comparison result register cmpreg. the initial values of the cmpreg are undefined and the comparator operation is disabled by a reset . the comparator has following components: ? comparator ? internal reference voltage generator (4-bit resolution) ? external reference voltage source at p2.3 ? comparator mode register (cmod) ? comparison result register (cmpreg)
comparator ks57c 0502/c0504/p0504 microcontroller 12? 2 p2.0 / cin0 p2.1 / cin1 p2.2 / cin2 p2.3 / cin3 comparison result register (cmpreg) 8 m u x v dd 1/2r r r 1/2r cmod.7 cmod.6 cmod.5 0 cmod.3 cmod.2 cmod.1 cmod.0 v ref (internal) + ? internal bus m u x 4 m u x v ref (external) figure 12?1. comparator circuit diagram
ks57c 0502/c0504/p0504 microcontroller comparator 12? 3 comparator mode register (cmod) the comparator mode register cmod is an 8-bit register that is used to set the operation mode of the comparator. it is mapped to addresses fd6h?fd7h and can be manipulated using 8-bit memory instructions. based on the cmod.5 bit setting, an internal or an external reference voltage is input for the comparator, as follows: when cmod.5 is set to logic zero: ? a reference voltage is selected by the cmod.0 to cmod.3 bit settings. ? p2.0 to p2.3 are used as analog input pins. ? the internal digital to analog converter generates 16 reference voltages. ? the comparator can detect 150 mv difference between the reference voltage and the analog input voltages. ? comparator results are written into 4-bit comparison result register (cmpreg). when cmod.5 is set to logic one: ? an external reference voltage is supplied from p2.3/cin3. ? p2.0 to p2.2 are used as the analog input pins. ? the comparator can detect 150 mv difference between the reference voltage and the analog input voltages. ? bits 0 ?2 in the cmpreg register contain the results; the content of bit 3 is not used. bit 6 in the cmod register controls conversion time while bit 7 enables or disables comparator operation to reduce power consumption. a reset signal clears all bits to logic zero, causing the comparator operation to enter stop mode. cmod.7 cmod.6 cmod.5 0 cmod.3 cmod.2 cmod.1 cmod.0 1: cin3; external reference, cin0?2; analog input 0: internal reference, cin0?3; analog input reference voltage (v ref ) selection: vdd x (n + 0.5)/16, n = 0 to 15 1: conversion time (4 x 2 /fx, 15.2 s @4.19mhz) 0: conversion time (4 x 2 /fx, 121.6 s @4.19mhz) 1: comparator operation enable 0: comparator operation disable 4 7 fd6h?fd7h figure 12?2. comparator mode register organization
comparator ks57c 0502/c0504/p0504 microcontroller 12? 4 port 2 mode register (p2mod) p2mod register settings determine if port 2 is used for analog or digital input. the p2mod register is 4-bit write only register. p2mod is mapped to address fe2h and initialized to logic zero by a reset , which configures port 2 as an analog input port. fe2h p2mod.3 p2mod.2 p2mod.1 p2mod.0 when bit is set to "1", the corresponding pin is configured as a digital input pin. when set to "0", configured as an analog input pin: p2mod.0 for p2.0, p2mod.1 for p2.1, p2mod.2 for p2.2, and p2mod.3 for p2.3. comparator operation the comparator compars analog voltage input at cin0?cin3 with an external or internal reference voltage (v ref ) that is selected by cmod register. the result is written to the comparison result register cmpreg at address fd4h. the comparison result is calculated as follows. if "1" analog input voltage 3 v ref + 150 mv if "0" analog input voltage v ref ? 150 mv to obtain a comparison result, the data must be read out from the cmpreg register after v ref is updated by changing the cmod value after a conversion time has elapsed. analog input voltage (cin0?3) reference voltage (v ref ) comparator clock (cmpclk, fx/16, fx/128) comparison result (cmpreg) comparison time (cmpclk x 4) comparison end 1 0 comparison start unknown 1 figure 12?3. conversion characteristics
ks57c 0502/c0504/p0504 microcontroller comparator 12? 5 + + programming tip ? programming the comparator the following code converts the analog voltage input at cin0?cin2 pins into 4-bit digital code. bitr emb ld a,#0h ld p2mod,a ; analog input selection (cin0 ?cin3) ld ea,#8xh ; x = 0 ?f, comparator enable ; internal reference, conversion time (121.6 s) ld cmod,ea wait ld a,#0h incs a jr wait ld a,cmpreg ; read the result ld p4,a ; output the result from port 4
comparator ks57c 0502/c0504/p0504 microcontroller 12? 6 notes
ks57c 0502/c0504/p0504 microcontroller serial i/o interface 13? 1 13 serial i/o interface overview the serial i/o interface (sio) has the following functional components: ? 8-bit mode register (smod) ? clock selector circuit ? 8-bit buffer register (sbuf) ? 3-bit serial clock counter using the serial i/o interface, you can exchange 8-bit data with an external device. you control the transmission frequency by the appropriate bit settings to the smod register. the serial interface can run off an internal or an external clock source, or the tol0 signal that is generated by the 8-bit timer/counter 0, tc0. if you use the tol0 clock signal, you can modify its frequency to adjust the serial data transmission rate.
serial i/o interface ks57c 0502/c0504/p0504 microcontroller 13? 2 sio operation sequence the general sequence of operations for the serial i/o interface may be summarized as follows: 1. set sio mode to transmit-and-receive or to receive-only. 2. select msb-first or lsb-first transmission mode. 3. set the sck clock signal in the mode register, smod. 4. set sio interrupt enable flag (ies) to "1". 5. initiate sio transmission by setting bit 3 of the smod to "1". 6. when the sio operation is complete, irqs flag is set and an interrupt is generated. internal bus lsb or msb first si irqs clk clk clk clear sck tol0 fx/2 10 fx/2 so 8 8 sbuf (8-bit) clock selector r q d q0 q1 q2 3-bit counter r s q smod.7 smod.6 smod.5 ? smod.3 smod.2 smod.1 smod.0 figure 13?1. serial i/o interface circuit diagram
ks57c 0502/c0504/p0504 microcontroller serial i/o interface 13? 3 serial i/o mode register (smod) the serial i/o mode register, smod, is an 8-bit register that specifies the operation mode of the serial interface. smod is mapped to ram address fe0h?fe1h and its reset value is logic zero. smod is organized in two 4-bit registers, as follows: fe0h smod.3 smod.2 smod.1 smod.0 fe1h smod.7 smod.6 smod.5 0 smod register settings enable you to select either msb-first or lsb-first serial transmission, and to operate in transmit-and-receive mode or receive-only mode. smod is a write-only register and can be addressed only by 8-bit ram control instructions. one exception to this is smod.3, which can be written by a 1-bit ram control instruction. when smod.3 is set to 1, the contents of the serial interface interrupt request flag, irqs, and the 3-bit serial clock counter are cleared, and sio operations are initiated. when the sio transmission starts, smod.3 is cleared to logic zero. table 13?1. sio mode register (smod) organization smod.0 0 most significant bit (msb) is transmitted first 1 least significant bit (lsb) is transmitted first smod.1 0 receive-only mode; output buffer is off 1 transmit-and-receive mode smod.2 0 disable the data shifter and clock counter; retain contents of irqs flag when serial transmission is halted 1 enable the data shifter and clock counter; set irqs flag to "1" when serial transmission is halted smod.3 1 clear irqs flag and 3-bit clock counter to "0"; initiate transmission and then reset this bit to logic zero smod.4 0 bit not used; value is always "0" smod.7 smod.6 smod.5 clock selection r/w status of sbuf 0 0 0 external clock at sck pin sbuf is enabled when sio operation is halted or when sck goes high. 0 0 1 use tol0 clock from tc0 0 1 x cpu clock: fx/4, fx/8, fx/64 enable sbuf read/write 1 0 0 4.09 khz clock: fx/2 10 sbuf is enabled when sio operation is halted or when sck goes high. 1 1 1 262 khz clock: fx/2 4 notes : 1. ' fx' = system clock; 'x' means 'don't care.' 2. khz frequency ratings assume a system clock ( fx) running at 4.19 mhz. 3. the sio clock selector circuit cannot select a fx/2 4 clock if the cpu clock is fx/64 .
serial i/o interface ks57c 0502/c0504/p0504 microcontroller 13? 4 serial i/o timing diagrams sck si so irqs di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 transmit complete set smod.3 figure 13?2. sio timing in transmit/receive mode high impedance sck si irqs transmit complete set smod.3 di7 di6 di5 di4 di3 di2 di1 di0 so figure 13?3. sio timing in receive-only mode
ks57c 0502/c0504/p0504 microcontroller serial i/o interface 13? 5 serial i/o buffer register (sbuf) when the serial interface operates in transmit-and-receive mode (smod.1 = "1"), transmit data in the sio buffer register are output to the so pin (p0.1) at the rate of one bit for each falling edge of the sio clock. receive data is simultaneously input from the si pin (p0.2) to sbuf at the rate of one bit for each rising edge of the sio clock. when receive-only mode is used, incoming data is input to the sio buffer at the rate of one bit for each rising edge of the sio clock. sbuf can be read or written using 8-bit ram control instructions. it is mapped to addresses fe4h?fe5h. following a reset , the value of sbuf is undetermined. + + programming tip ? setting transmit/receive modes for serial i/o 1. transmit the data value 48h through the serial i/o interface using an internal clock f requency of fx/2 4 and in msb-first mode: bits emb smb 15 ld ea,#03h ld pmg1,ea ; p0.0 / sck and p0.1 / so ? output ld ea,#48h ; ld sbuf,ea ; ld ea,#0eeh ld smod,ea ; sio data transfer external device sck / p0.0 so / p0.1 2. use cpu clock to transfer and receive serial data at high speed: bits emb smb 15 ld ea,#03h ld pmg1,ea ; p0.0 / sck and p0.1 / so ? output, p0.2 / si ? input ld ea,tdata ld sbuf,ea ld ea,#4fh ld smod,ea ; sio start bitr ies stest btstz irqs jr stest ld ea,sbuf smb 0 ld rdat a,ea
serial i/o interface ks57c 0502/c0504/p0504 microcontroller 13? 6 + + programming tip ? setting transmit/receive modes for serial i/o (continued) 3. transmit and receive an internal clock frequency of 4.09 khz (at 4.19 mhz) in lsb-first mode: bits emb smb 15 ld ea,#03h ld pmg1,ea ; p0.0 / sck and p0.1 / so ? output, p0.2/si ? input ld ea,tdata ld sbuf,ea ld ea,#8fh ld smod,ea ; sio start ei bits ies ? ? ints push sb ; store smb, srb push ea ; sto re ea ld ea,tdata ; ea ? transmit data smb 15 xch ea,sbuf ; ea ? receive data smb 0 ld rdata,ea ; rdata ? receive data bits smod.3 ; sio start pop ea pop sb iret external device sck / p0.0 so / p0.1 si / p0.2
ks57c 0502/c0504/p0504 microcontroller serial i/o interface 13? 7 + + programming tip ? setting transmit/receive modes for serial i/o (continued) 4. transmit and receive an external clock in lsb-first mode: bits emb smb 15 ld ea,#02h ld pmg1,ea ; p0.1 / so ? output, p0.0 / sck and p0.2 / si ? input ld ea,tdata ld sbuf,ea ld ea,#0fh ld smod,ea ; sio start ei bits ies ? ? ints push sb ; store smb, srb push ea ; store ea ld ea,tdata ; ea ? transmit data smb 15 xch ea,sbuf ; ea ? receive data smb 0 ld rdata,ea ; rdata ? receive data bits smod.3 ; sio start pop ea pop sb iret external device sck / p0.0 so / p0.1 si / p0.2 high speed sio transmission
serial i/o interface ks57c 0502/c0504/p0504 microcontroller 13? 8 + + programming tip ? setting transmit/receive modes for serial i/o (concluded) use cpu clock to transfer and receive serial data at high speed: bits emb smb 15 ld ea,#03h ld pmg1,ea ; p0.0 / sck and p0.1 / so ? output, p0.2 / si ? input ld ea,tdata ld sbuf,ea ld ea,#4fh ld smod,ea ; sio start bitr ies stest btstz irqs jr stest ld ea,sbuf smb 0 ld rdata,ea
ks57c 0502/c0504/p0504 microcontroller electrical data 14? 1 14 electrical data table 14? 1. absolute maximum ratings (t a = 25 c ) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 5 ma all i/o ports active ? 15 output current low i ol ports 0, 3, and 6 5 ma ports 4 and 5 30 all ports, total + 100 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c table 14? 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 ports 4 and 5 0.7v dd ? v dd v v ih2 ports 0, 1, 2, 3, 6, and reset 0.8v dd ? v dd v ih3 x in and x out v dd ? 0. 1 ? v dd input low voltage v il1 ports 4 and 5 ? ? 0.3v dd v v il2 ports 0, 1, 2, 3, 6, and reset 0.2v dd v il3 x in and x out 0.1 output high voltage v oh v dd = 4.5 v to 5.5 v i oh = ? 1 ma ports 0, 3, 4, 5, 6 v dd - 1.0 ? ? v
electrical data ks57c 0502/c0504/p0504 microcontroller 14? 2 table 14? 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output low voltage v ol v dd = 4.5 v to 5.5 v i ol = 15 ma ports 4, 5 ? ? 2 v v dd = 4.5v to 5.5 v i ol = 4.0ma all output pins except ports 4, 5 ? 2 input high leakage current i lih1 v in = v dd all input pins except x in and x out ? ? 3 m a i lih2 v in = v dd x in and x out 20 input low leakage current i lil1 v in = 0 v all input pins except x in , x out and reset ? ? ? 3 m a i lil2 v in = 0 v x in and x out ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 m a output low leakage current i lol v o = 0 v ? ? ? 3 m a pull-up resistor r l1 v i = 0 v; v dd = 5 v port 0, 1, 3, 4, 5, 6 25 50 100 k w v dd = 3 v 50 100 200 r l 2 v dd = 5 v ; v i = 0 v ; reset 100 250 400 v dd = 3 v 200 500 800
ks57c 0502/c0504/p0504 microcontroller electrical data 14? 3 table 14? 2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units supply i dd1 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 3.0 8.0 ma current (1) crystal oscillator; c1=c2=22pf 4.19mhz 2.0 5.5 v dd = 3 v 10% 6.0mhz 1.3 4.0 4.19mhz 1.0 3.0 i dd 2 idle mode; v dd = 5.0 v 1 0% 6.0mhz ? 0.8 2.5 ma crystal oscillator; c1=c2=22pf 4.19mhz 0.6 1.8 v dd = 3 v 10% 6.0mhz 0.6 1.5 4.19mhz 0.4 1.0 i dd3 stop mode; v dd = 5.0 v 1 0% ? 0.5 3.0 m a stop mode; v dd = 3.0 v 1 0% 0.3 2.0 notes: 1. d.c. electrical values for supply current ( i dd1 to i dd3 ) do not include current drawn through internal pull-up registers, output port drive currents and comparator. 2. the supply current assumes a cpu clock of fx/4. cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) supply voltage (v) 1.05 mhz 15.625 khz cpu clock 4.2 mhz 6 mhz 400 khz main osc. freq. ( divided by 4 ) 1.5 mhz 1 2 2.7 3 4 5 6 7 figure 14? 1. standard operating voltage range
electrical data ks57c 0502/c0504/p0504 microcontroller 14? 4 table 14? 3. oscillators characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5 . 5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3.0 v ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3.0 v ? ? 10 ms external clock xin xout x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 4.2 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
ks57c 0502/c0504/p0504 microcontroller electrical data 14? 5 table 14? 4. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out 15 pf i/o capacitance c io 15 pf table 14? 5. comparator electrical characteristics (t a = ? 40 c to + 85 c, v dd = 4.0 v to 5.5 v, v ss = 0 v) parameter symbol condition min typ max units input voltage range ? ? 0 ? v dd v reference voltage range v ref ? 0 ? v dd v input voltage accuracy v cin ? ? ? 150 mv input leakage current i cin, i ref ? ? 3 ? 3 m a table 14? 6. a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1 . 8 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time t cy v dd = 2.7 v to 5.5 v 0. 67 ? 64 m s v dd = 1.8 v to 5.5 v 0.95 tcl0 input frequency f ti v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 1.8 v to 5.5 v 1 mhz tcl0 input high, low width t tih , t til v dd = 2.7 v to 5.5 v 0.48 ? ? m s v dd = 1.8 v to 5.5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v external sck source 800 ? ? ns internal sck source 670 v dd = 1.8 v to 5.5 v external sck source 3200 internal sck source 3800
electrical data ks57c 0502/c0504/p0504 microcontroller 14? 6 table 14?6 . a.c. electrical characteristics ( concluded ) (t a = ? 40 c to + 85 c, v dd = 1 . 8 v to 5.5 v) parameter symbol conditions min typ max units sck high, low width t kh , t kl v dd = 2 . 7 v to 5.5 v external sck source 335 ? ? ns internal sck source t kcy /2 - 50 v dd = 1.8 v to 5.5 v external sck source 1600 internal sck source t kcy / 2 - 150 si setup time to sck high t sik v dd = 2 . 7 v to 5.5 v external sck source 100 ? ? ns internal sck source 150 v dd = 1.8 v to 5.5 v external sck source 150 internal sck source 500 si hold time to sck high t ksi v dd = 2 . 7 v to 5.5 v external sck source 400 ? ? ns internal sck source 400 v dd = 1.8 v to 5.5 v external sck source 600 internal sck source 500 output delay for sck to so t kso (1) v dd = 2 . 7 v to 5.5 v external sck source ? ? 300 ns internal sck source 250 v dd = 1.8 v to 5.5 v external sck source 1000 internal sck source 1000 interrupt input high, low width t inth , t intl int0 ( 2) ? ? m s int1, ks0 - ks2 10 reset input low width t rsl input 10 ? ? m s note s : 1. r(1kohm) and c (100pf) are the load resistance and load capacitance of the so output line. 2. minimum value for int0 is based on a clock of 2t cy or 128 / fx as assigned by the imod0 register setting.
ks57c 0502/c0504/p0504 microcontroller electrical data 14? 7 table 14-7 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.8 ? 5.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 m a release signal set time t srel ? 0 ? ? m s oscillator stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? ms notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability duri ng oscillator start- up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu ins tructions during the wait time. timing waveforms t srel t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset operation idle mode operating mode figure 14?2. stop mode release timing when initiated by reset
electrical data ks57c 0502/c0504/p0504 microcontroller 14? 8 v dd execution of stop instruction v dddr data retention mode stop mode t wait t srel idle mode normal operating mode power-down mode terminating signal (interrupt request) figure 14? 3. stop mode release timing when initiated by interrupt request measurement points 0.8 vdd 0.8 vdd 0.2 vdd 0.2 vdd figure 14? 4. a.c. timing measurement points (except for x in ) xin t xl t xh 1 / fx 0.2 v vdd - 0.2 v figure 14?5 . clock timing measurement at x in
ks57c 0502/c0504/p0504 microcontroller electrical data 14? 9 tcl t til t tih 1 / f ti 0.8 vdd 0.2 vdd figure 14? 6. tcl timing t rsl reset 0.2 v dd figure 14?7 . input timing for reset signal int0, 1 ks0 to ks2 t intl t inth 0.2 vdd 0.8 vdd figure 14? 8. input timing for external interrupts
electrical data ks57c 0502/c0504/p0504 microcontroller 14? 10 sck t kl t kh t cky 0.8 v dd input data output data 0.2 v dd 0.8 v dd 0.2 v dd si so t sik t ksi t kso figure 14?9 . serial data transfer timing
ks57c 0502/0504/p0504 microcontroller mec hanical data 15 ? 1 15 mechanical data this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram ? pad/pin coordinate data table note : typical dimensions are in millimeters. 30-sdip-400 8.94 0.2 0.56 0.1 27.48 0.2 0 ~ 15 0.25 +0.1 ? 0.05 #1 15 30 16 10.16 (1.30) 1.12 0.1 1.778 0.51min 3.81 0.2 3.30 0.3 5.08max figure 15?1. 30-sdip-400 package dimensions
mechanical data ks57 c 0502/0504/p0504 microcontroller 15? 2
KS57C0502/c0504/p0504 microcontroller ks57p0504 otp 16? 1 16 ks57p0504 otp overview the ks57p0504 single-chip cmos microcontroller is the otp (one time programmable) version of the KS57C0502/c0504 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the ks57p0504 is fully compatible with the KS57C0502/c0504, both in function and in pin configuration. because of its simple programming requirements, the ks57p0504 is ideal for use as an evaluation chip for the KS57C0502/c0504. vdd / vdd p6.3 / buz / sclk p6.2 / ks2 / sdat p6.1 / ks1 p6.0 / ks0 p5.3 p5.2 p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 p3.2 / clo p3.1 / tclo0 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vss / vss xout xin test / test p1.0 / int0 p1.1 / int1 reset / reset p0.0 / sck p0.1 / so p0.2 / si p2.0 / cin0 p2.1 / cin1 p2.2 / cin2 p2.3 / cin3 p3.0 / tcl0 ks57p0504 (30-sdip) note: the bolds indicate an otp pin name. figure 16?1. ks57p0504 pin assignments (30-sdip package)
ks57p0504 otp KS57C0502/c0504/p05 04 microcontroller 16? 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v ss xout xin test p1.0 / int0 p1.1 / int1 reset nc p0.0 / sck p0.1 / so p0.2 / si p2.0 / cin0 p2.1 / cin1 p2.2 / cin2 p2.3 / cin3 p3.0 / tcl0 v dd / vdd p6.3 / buz / sclk p6.2 / ks2 / sdat p6.1 / ks1 p6.0 / ks0 p5.3 p5.2 p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 nc p3.2 / clo p3.1 / tclo0 ks57p0504 (32-sop) note: the bolds indicate an otp pin name. vss / v ss xout xin test / test p1.0 / int0 p1.1 / int1 reset / reset nc p0.0 / sck p0.1 / so p0.2 / si p2.0 / cin0 p2.1 / cin1 p2.2 / cin2 p2.3 / cin3 p3.0 / tcl0 figure 16?2. ks57p0504 pin assignments (32-sop package)
KS57C0502/c0504/p0504 microcontroller ks57p0504 otp 16? 3 table 16?1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p6.2 sdat 28 (30) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. p6.3 sclk 29 (31) i/o serial clock pin. input only pin. test v pp (test) 4 (4) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 7 (7) i chip initialization v dd / v ss v dd / v ss 30/1 (32/1) i logic power supply pin. v dd should be tied to +5 v during programming. note: ( ) means the 32-sop otp pin number. table 16?2. comparison of ks57p0504 and KS57C0502/c0504 features characteristic ks57p0504 KS57C0502/c0504 program memory 4 k-byte eprom 2 k-byte mask rom: KS57C0502 4 k-byte mask rom: ks57c0504 operating voltage (v dd ) 2.0 v to 5.5 v 1.8 v to 5.5v otp programming mode v dd = 5 v, v pp (test)=12.5v ? pin configuration 30 sdip, 32 sop 30 sdip, 32 sop eprom programmability user program one time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the ks57p0504, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16?3 below. table 16?3. operating mode selection criteria v dd vpp (test) reg/ mem address (a15-a0) r/ w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
ks57p0504 otp KS57C0502/c0504/p05 04 microcontroller 16? 4 otp electrical data table 16?4 . absolute maximum ratings (t a = 25 c ) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 5 ma all i/o ports active ? 15 output current low i ol ports 0, 3, and 6 5 ma ports 4 and 5 30 all ports, total + 100 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c table 16?5 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 ports 4 and 5 0.7v dd ? v dd v v ih2 ports 0, 1, 2, 3, 6, and reset 0.8v dd ? v dd v ih3 x in and x out v dd ? 0. 1 ? v dd input low voltage v il1 ports 4 and 5 ? ? 0.3v dd v v il2 ports 0, 1, 2, 3, 6, and reset 0.2v dd v il3 x in and x out 0.1 output high voltage v oh v dd = 4.5 v to 5.5 v i oh = ? 1 ma ports 0, 3, 4, 5, 6 v dd - 1.0 ? ? v
KS57C0502/c0504/p0504 microcontroller ks57p0504 otp 16? 5 table 16?5 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units output low voltage v ol v dd = 4.5 v to 5.5 v i ol = 15 ma ports 4, 5 ? ? 2 v v dd = 4.5v to 5.5 v i ol = 4.0ma all output pins except ports 4, 5 ? 2 input high leakage current i lih1 v in = v dd all input pins except x in and x out ? ? 3 m a i lih2 v in = v dd x in and x out 20 input low leakage current i lil1 v in = 0 v all input pins except x in , x out and reset ? ? ? 3 m a i lil2 v in = 0 v x in and x out ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 m a output low leakage current i lol v o = 0 v ? ? ? 3 m a pull-up resistor r l1 v i = 0 v; v dd = 5 v port 0, 1, 3, 4, 5, 6 25 50 100 k w v dd = 3 v 50 100 200 r l 2 v dd = 5 v ; v i = 0 v ; reset 100 250 400 v dd = 3 v 200 500 800
ks57p0504 otp KS57C0502/c0504/p05 04 microcontroller 16? 6 table 16?5 . d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units supply i dd1 run mode; v dd = 5.0 v 1 0% 6.0mhz ? 3.0 8.0 ma current (1) crystal oscillator; c1=c2=22pf 4.19mhz 2.0 5.5 v dd = 3 v 10% 6.0mhz 1.3 4.0 4.19mhz 1.0 3.0 i dd 2 idle mode; v dd = 5.0 v 1 0% 6.0mhz ? 0.8 2.5 ma crystal oscillator; c1=c2=22pf 4.19mhz 0.6 1.8 v dd = 3 v 10% 6.0mhz 0.6 1.5 4.19mhz 0.4 1.0 i dd3 stop mode; v dd = 5.0 v 1 0% ? 0.5 3.0 m a stop mode; v dd = 3.0 v 1 0% 0.3 2.0 notes: 1. d.c. electrical values for supply current ( i dd1 to i dd3 ) do not include current drawn through internal pull-up registers, output port drive currents and comparator. 2. the supply current assumes a cpu clock of fx/4. cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) supply voltage (v) 1.05 mhz 15.625 khz cpu clock 4.2 mhz 6 mhz 400 khz main osc. freq. ( divided by 4 ) 1.5 mhz 1 2 2.7 3 4 5 6 7 figure 16?3 . standard operating voltage range
KS57C0502/c0504/p0504 microcontroller ks57p0504 otp 16? 7 table 16?6 . oscillators characteristics (t a = ? 40 c + 85 c, v dd = 2.0 v to 5 . 5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3.0 v ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3.0 v ? ? 10 ms external clock xin xout x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5 v 0.4 ? 4.2 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
ks57p0504 otp KS57C0502/c0504/p05 04 microcontroller 16? 8 table 16?7 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out 15 pf i/o capacitance c io 15 pf table 16?8 . comparator electrical characteristics (t a = ? 40 c to + 85 c, v dd = 4.0 v to 5.5 v, v ss = 0 v) parameter symbol condition min typ max units input voltage range ? ? 0 ? v dd v reference voltage range v ref ? 0 ? v dd v input voltage accuracy v cin ? ? ? 150 mv input leakage current i cin, i ref ? ? 3 ? 3 m a table 16?9 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time t cy v dd = 2.7 v to 5.5 v 0. 67 ? 64 m s v dd = 2.0 v to 5.5 v 0.95 tcl0 input frequency f ti v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 2.0 v to 5.5 v 1 mhz tcl0 input high, low width t tih , t til v dd = 2.7 v to 5.5 v 0.48 ? ? m s v dd = 2.0 v to 5.5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v external sck source 800 ? ? ns internal sck source 670 v dd = 2.0 v to 5.5 v external sck source 3200 internal sck source 3800
KS57C0502/c0504/p0504 microcontroller ks57p0504 otp 16? 9 table 16?9 . a.c. electrical characteristics ( concluded ) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units sck high, low width t kh , t kl v dd = 2 . 7 v to 5.5 v external sck source 335 ? ? ns internal sck source t kcy /2 - 50 v dd = 2.0 v to 5.5 v external sck source 1600 internal sck source t kcy / 2 - 150 si setup time to sck high t sik v dd = 2 . 7 v to 5.5 v external sck source 100 ? ? ns internal sck source 150 v dd = 2.0 v to 5.5 v external sck source 150 internal sck source 500 si hold time to sck high t ksi v dd = 2 . 7 v to 5.5 v external sck source 400 ? ? ns internal sck source 400 v dd = 2.0 v to 5.5 v external sck source 600 internal sck source 500 output delay for sck to so t kso (1) v dd = 2 . 7 v to 5.5 v external sck source ? ? 300 ns internal sck source 250 v dd = 2.0 v to 5.5 v external sck source 1000 internal sck source 1000 interrupt input high, low width t inth , t intl int0 ( 2) ? ? m s int1, ks0 - ks2 10 reset input low width t rsl input 10 ? ? m s note s : 1. r(1kohm) and c (100pf) are the load resistance and load capacitance of the so output line. 2. minimum value for int0 is based on a clock of 2t cy or 128 / fx as assigned by the imod0 register setting.
ks57p0504 otp KS57C0502/c0504/p05 04 microcontroller 16? 10 table 16?10 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 2.0 ? 5.5 v data retention supply current i dddr v dddr = 2.0 v ? 0.1 10 m a release signal set time t srel ? 0 ? ? m s oscillator stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? ms notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu ins tructions during the wait time.
KS57C0502/c0504/p0504 microcontroller ks57p0504 otp 16? 11 start address= first location v dd =5v, v pp =12.5v x = 0 program one 1ms pulse increment x x = 10 verify 1 byte last address v dd = v pp = 5 v compare all byte device passed increment address verify byte device failed pass fail no fail yes fail no figure 16?4. otp programming algorithm
ks57p0504 otp KS57C0502/c0504/p05 04 microcontroller 16? 12 notes
KS57C0502/c0504/p0504 microcontroller development tools 17? 1 17 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for ks57, ks86, ks88 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, as s embler, and a program for setting options. shine samsung host interface for in - c ircuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm 57 the sasm 57 is an relocatable assembler for samsung's ks 57 -series microcontrollers. the sasm 57 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm 57 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value 'ff' is filled into the unused rom area upto the maximum rom size of the target device automatically. target boards target boards are available for all ks 57 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board. otp s one time programmable microcontroller ( otp) for the KS57C0502/c0504 microcontroller and otp programmer (gang) are now available.
development tools KS57C0502/c0504/p0 504 microcontroller 17? 2 ram break/ display unit target application system probe adapter tb570502a/0504a target board prom/mtp writer unit trace/timer unit sam4 base unit power supply unit pod rs-232c ibm-pc at or compatible bus smds2+ eva chip figure 17?1 . smds product configuration (smds2+)
KS57C0502/c0504/p0504 microcontroller development tools 17? 3 tb570502a/0504a target board the tb570502a/0504a target board is used for the KS57C0502/c0504/p0504 microcontroller. it is supported by the smds2+ development system. sm1253a tb570502a/0504a 3 0-pin connector 1 30 15 16 1 25 external triggers ch1 ch2 off on to user_vcc reset + stop + idle 100-pin connector j101 100 qfp ks57e0500 eva chip 1 30 74hc11 xtal mds xi figure 17?2 . tb570502a/tb570504a target board configuration
development tools KS57C0502/c0504/p0 504 microcontroller 17? 4 table 17?1. power selection settings for tb570502a/tb570504a 'to user_vcc' settings operating mode comments to user_vcc on off v cc target system smds2/smds2+ v ss v cc tb570502a /0504a the smds2 /smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_vcc on off target system external v cc smds2/smds2+ v cc v ss tb570502a /0504a the smds2 /smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. table 17 ? 2. clock selection settings for tb570502a/tb570504a sub clock setting operating mode comments xti xtal mds xt in smds2/ smds2+ eva chip ks57e 0500 xt out no connection 100 pin connector set the xti switch to ?mds? when the target board is connected to the smds2/smds2+. xti xtal mds xt in target board eva chip ks57e0500 xt out xtal set the xti switch to ?xtal? when the target board is used as a standalone unit, and is not connected to the smds2/smds2+.
KS57C0502/c0504/p0504 microcontroller development tools 17? 5 table 17?3 . using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the smds2+ breakpoint and trace functions. idle led this led is on when the evaluation chip (ks 57e0500 ) is in idle mode. stop led this led is on when the evaluation chip (ks 57e0500 ) is in stop mode.
development tools KS57C0502/c0504/p0 504 microcontroller 17? 6 j101 v ss xout xin test p1.0/int0 p1.1/int1 reset p0.0/ sck p0.1/so p0.2/si p2.0/cin0 p2.1/cin1 p2.2/cin2 p2.3/cin3 p3.0/tcl0 v dd p6.3/buz/ sclk p6.2/ks2/sdat p6.1/ks1 p6.0/ks0 p5.3 p5.2 p5.1 p5.0 p4.3 p4.2 p4.1 p4.0 p3.2/clo p3.1/tclo0 3 0-pin dip connector 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 figure 17?3 . 3 0-pin connector for tb570502a/tb570504a 3 0-pin dip connector target board target system target cable for 32-sdip socket part name: ap30sd-c order code: sm6519 j101 1 30 15 16 1 30 15 16 figure 17?4 . tb570502a/tb570504a adapter cable for 3 0 -s di p package ( KS57C0502/c0504/p0504 )

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